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| author | Tim Newsome <tim@sifive.com> | 2018-07-17 13:38:26 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2019-03-04 09:19:10 -0800 |
| commit | 9a2904a97a1b157386555ec134e2f9b8f365ec36 (patch) | |
| tree | 3d0f1bb65d29b109f5466d318a1c76c77687e169 /debug_rom/debug_rom.S | |
| parent | f9d2be538b134ac42bf33b4b04e97d182ced5e36 (diff) | |
| download | riscv-isa-sim-debug_rom.zip riscv-isa-sim-debug_rom.tar.gz riscv-isa-sim-debug_rom.tar.bz2 | |
Clean up/optimize Debug ROM.debug_rom
It's 3 instructions shorter now.
Diffstat (limited to 'debug_rom/debug_rom.S')
| -rwxr-xr-x | debug_rom/debug_rom.S | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index 28c7076..f60b367 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -12,11 +12,10 @@ // their GO or RESUME bit is set. entry: - jal zero, _entry -resume: - jal zero, _resume + jal zero, _entry exception: - jal zero, _exception + sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. + // fall through to _entry _entry: // This fence is required because the execution may have written something @@ -40,10 +39,6 @@ entry_loop: bnez s0, resume jal zero, entry_loop -_exception: - sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception. - ebreak - going: csrr s0, CSR_DSCRATCH // Restore s0 here sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset. @@ -53,7 +48,7 @@ going: // so we use fence and fence.i for safety. (rocket-chip doesn't have this // because jalr is special there) -_resume: +resume: csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset. csrr s0, CSR_DSCRATCH // Restore s0 |