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| author | Andrew Waterman <andrew@sifive.com> | 2025-12-09 09:29:18 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-12-09 09:29:18 -0800 |
| commit | abb0d9873878268c0293edf20dcd8877f767a863 (patch) | |
| tree | 9abd2665300ea878d1ac85ee0e5676a74f181c17 | |
| parent | 59bf54676e0a2323bc5cb4a163fd3aca7f857ec3 (diff) | |
| parent | b4854c14934fda999f8d9b24ea692021c58787af (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
Fix VS-mode check for sireg* (really vsireg*) CSRs
| -rw-r--r-- | riscv/csrs.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 70468d0..914662a 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1866,7 +1866,7 @@ void sscsrind_reg_csr_t::verify_permissions(insn_t insn, bool write) const { } if (proc->extension_enabled(EXT_SMCDELEG)) { - if (insn.csr() >= CSR_VSIREG && insn.csr() <= CSR_VSIREG6) { + if (address >= CSR_VSIREG && address <= CSR_VSIREG6) { if (!state->v) { // An attempt to access any vsireg* from M or S mode raises an illegal instruction exception. throw trap_illegal_instruction(insn.bits()); @@ -1884,7 +1884,7 @@ void sscsrind_reg_csr_t::verify_permissions(insn_t insn, bool write) const { } } } - if (insn.csr() >= CSR_SIREG && insn.csr() <= CSR_SIREG6) { + if (address >= CSR_SIREG && address <= CSR_SIREG6) { // attempts to access any sireg* when menvcfg.CDE = 0; if ((state->menvcfg->read() & MENVCFG_CDE) != MENVCFG_CDE) { if (!state->v) { |