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2014-04-07Update riscv-opcodes. Other correspondent projects made consistent.Stephen Twigg1-0/+0
2014-03-08Add fclass.{s|d} instructionsAndrew Waterman1-0/+0
2014-03-03update testsYunsup Lee1-0/+0
2014-03-02sync up gcc,isa-sim,opcodes,pk,testsYunsup Lee1-0/+0
2014-02-27push testsYunsup Lee1-0/+0
2014-02-27push testsYunsup Lee1-0/+0
2014-02-25push testsYunsup Lee1-0/+0
2014-02-14Renumber uarch CSRs into custom CSR spaceAndrew Waterman1-0/+0
2014-02-10Revert to old AUIPC definitionAndrew Waterman1-0/+0
2014-02-06push gcc,spike,pk,testsYunsup Lee1-0/+0
2014-02-06Add support for uarch-specific performance countersAndrew Waterman1-0/+0
2014-02-03Remove vsetprec and add vfmsv, vfmvvQuan Nguyen1-0/+0
2014-01-31Fix Darwin buildAndrew Waterman1-0/+0
2014-01-28Fix some bugs related to dynamic linkingAndrew Waterman1-0/+0
2014-01-21Generate CAUSE numbers from riscv-opcodes; add CSR testAndrew Waterman1-0/+0
2014-01-20Catch up to recent toolchain changesQuan Nguyen1-0/+0
2013-11-13getting ready for torture test generatorYunsup Lee1-0/+0
2013-11-05push isa-sim,pk,testsYunsup Lee1-0/+0
2013-10-18push isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-18push isa-sim,testsYunsup Lee1-0/+0
2013-10-17push gcc,isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-17push gcc,isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-10push gcc,isa-sim,opcodes,pk,testsYunsup Lee1-0/+0
2013-09-21Update testsAndrew Waterman1-0/+0
2013-09-21New ISA encodingAndrew Waterman1-0/+0
2013-06-10Fix Darwin build againAndrew Waterman1-0/+0
2013-05-13push riscv-isa-sim,riscv-testsYunsup Lee1-0/+0
2013-04-29add riscv-testsYunsup Lee1-0/+0
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