| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-02-03 | Remove vsetprec and add vfmsv, vfmvv | Quan Nguyen | 1 | -0/+0 |
| 2014-01-21 | Generate CAUSE numbers from riscv-opcodes; add CSR test | Andrew Waterman | 1 | -0/+0 |
| 2014-01-20 | Catch up to recent toolchain changes | Quan Nguyen | 1 | -0/+0 |
| 2013-11-29 | Add vsetprec instruction prototype | Quan Nguyen | 1 | -0/+0 |
| 2013-11-26 | Create confprec tool branch | Quan Nguyen | 1 | -0/+0 |
| 2013-10-29 | push opcodes | Yunsup Lee | 1 | -0/+0 |
| 2013-10-18 | push isa-sim,opcodes,tests | Yunsup Lee | 1 | -0/+0 |
| 2013-10-17 | push gcc,isa-sim,opcodes,tests | Yunsup Lee | 1 | -0/+0 |
| 2013-10-17 | push gcc,isa-sim,opcodes,tests | Yunsup Lee | 1 | -0/+0 |
| 2013-10-10 | push gcc,isa-sim,opcodes,pk,tests | Yunsup Lee | 1 | -0/+0 |
| 2013-09-21 | New ISA encoding | Andrew Waterman | 1 | -0/+0 |
| 2013-04-19 | push riscv-fesvr,riscv-gcc,riscv-isa-sim,riscv-opcodes,riscv-pk | Yunsup Lee | 1 | -0/+0 |
| 2012-03-24 | new supervisor mode | Andrew Waterman | 1 | -0/+0 |
| 2012-03-18 | update opcodes | Andrew Waterman | 1 | -0/+0 |
| 2012-03-18 | add riscv-opcodes submodule | Andrew Waterman | 1 | -0/+0 |
