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AgeCommit message (Expand)AuthorFilesLines
2017-03-23WIP on priv-1.10Andrew Waterman1-0/+0
2017-03-09WIP on priv-1.10Andrew Waterman1-0/+0
2017-01-04Delete obsolete references to JOBS variableAndrew Waterman1-0/+0
2016-08-26WIP on priv-1.9.1Andrew Waterman1-0/+0
2016-07-06Update to new PTE formatAndrew Waterman1-0/+0
2016-06-23Remove HTIFfreedom-unleashed-v0.1Andrew Waterman1-0/+0
2016-06-17remove sasid; bump testsAndrew Waterman1-0/+0
2016-06-09Update breakpoint specAndrew Waterman1-0/+0
2016-06-08Add provisional HW breakpoint supportAndrew Waterman1-0/+0
2016-06-01bump toolchainAndrew Waterman1-0/+0
2016-05-22more WIP on privileged arch v1.9Andrew Waterman1-0/+0
2016-05-03Update to gcc 6.1Andrew Waterman1-0/+0
2016-05-02Remove tohost/fromhost CSRsAndrew Waterman1-0/+0
2016-04-30ERET -> xRET; change memory mapAndrew Waterman1-0/+0
2016-03-14WIP on privileged spec v1.9Andrew Waterman1-0/+0
2015-11-25Use MMIO for device discoveryAndrew Waterman1-0/+0
2015-09-28bump submodulesScott Beamer1-0/+0
2015-08-18Upgrade to privileged architecture v1.7, sans qemuAndrew Waterman1-0/+0
2015-01-20update all reposAndrew Waterman1-0/+0
2014-10-24push isa-sim,opcodes,pk,testsYunsup Lee1-0/+0
2014-10-23Bump riscv-opcodesAlbert Ou1-0/+0
2014-04-07Update riscv-opcodes. Other correspondent projects made consistent.Stephen Twigg1-0/+0
2014-03-11Fix syntax error in generated opcodesAndrew Waterman1-0/+0
2014-03-11New FP encodingAndrew Waterman1-0/+0
2014-03-08Add fclass.{s|d} instructionsAndrew Waterman1-0/+0
2014-03-02sync up gcc,isa-sim,opcodes,pk,testsYunsup Lee1-0/+0
2014-02-14Renumber uarch CSRs into custom CSR spaceAndrew Waterman1-0/+0
2014-02-06Add support for uarch-specific performance countersAndrew Waterman1-0/+0
2014-02-03Remove vsetprec and add vfmsv, vfmvvQuan Nguyen1-0/+0
2014-01-21Generate CAUSE numbers from riscv-opcodes; add CSR testAndrew Waterman1-0/+0
2014-01-20Catch up to recent toolchain changesQuan Nguyen1-0/+0
2013-11-29Add vsetprec instruction prototypeQuan Nguyen1-0/+0
2013-11-26Create confprec tool branchQuan Nguyen1-0/+0
2013-10-29push opcodesYunsup Lee1-0/+0
2013-10-18push isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-17push gcc,isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-17push gcc,isa-sim,opcodes,testsYunsup Lee1-0/+0
2013-10-10push gcc,isa-sim,opcodes,pk,testsYunsup Lee1-0/+0
2013-09-21New ISA encodingAndrew Waterman1-0/+0
2013-04-19push riscv-fesvr,riscv-gcc,riscv-isa-sim,riscv-opcodes,riscv-pkYunsup Lee1-0/+0
2012-03-24new supervisor modeAndrew Waterman1-0/+0
2012-03-18update opcodesAndrew Waterman1-0/+0
2012-03-18add riscv-opcodes submoduleAndrew Waterman1-0/+0