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riscv-tools.git
bump-20180430
bump-debug
bump-spike
bump-tests-for-debug-priv
cs152-sp18-lab3
debug-fix-dontdeleteme
debug-user-niceness
debug_vcs_timeouts
faster_gdb_test
fesvr-dont-die
fesvr_dtm
master
merge
merge-priv-1.9
mmio-hack
more_timeout_fixes
mpsse_flush
new-abi
new_privileged_isa
newprogram
no_examine_target
openocd-enum
openocd-faster-sim
openocd-merge
openocd-no-progbuf
openocd_gdb_watchpoint
openocd_sba_option
priv-1.10
priv-1.9
privchange-dontdeleteme
project-template-compat
release
rvv
sim_remote_bitbang
test_rocket_chip_regression_build
tests-xlen
timsifive
tmp
usb_error
version_check
with_gdb
xlen_args
xml_registers
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Age
Commit message (
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Author
Files
Lines
2019-03-31
Remove the toolchain in riscv-tools
Palmer Dabbelt
1
-3
/
+0
2019-03-31
Merge fesvr into spike repo; bump spike to v1.0.0
Andrew Waterman
1
-3
/
+0
2018-01-22
Remove riscv-llvm
Palmer Dabbelt
1
-3
/
+0
2017-05-02
Add OpenOCD
Palmer Dabbelt
1
-0
/
+3
2016-02-10
Temporarily remove qemu from riscv-tools while rewriting qemu history.
Sagar Karandikar
1
-3
/
+0
2016-02-01
add qemu back to riscv-tools
Sagar Karandikar
1
-0
/
+3
2015-08-18
Upgrade to privileged architecture v1.7, sans qemu
Andrew Waterman
1
-3
/
+0
2015-02-07
Update module pointers to http://github.com/riscv/
Palmer Dabbelt
1
-8
/
+8
2014-12-03
New ABI/tool
Andrew Waterman
1
-3
/
+3
2014-07-29
add riscv-qemu, change submodule refs to https
Sagar Karandikar
1
-7
/
+10
2014-03-06
add riscv-llvm
Yunsup Lee
1
-0
/
+3
2013-04-29
add riscv-tests
Yunsup Lee
1
-0
/
+3
2012-03-18
add riscv-opcodes submodule
Andrew Waterman
1
-0
/
+3
2011-11-11
Update to new compiler toolchain
Your Name
1
-3
/
+3
2011-08-28
added riscv-isa-sim, riscv-fesvr, riscv-gcc-newlib, riscv-pk repos as submodules
Rimas Avizienis
1
-0
/
+12