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authorAndrew Waterman <andrew@sifive.com>2019-03-31 00:55:32 -0700
committerAndrew Waterman <andrew@sifive.com>2019-03-31 17:13:25 -0700
commit1d08559a0280a0b975381ea4a0591ecd9ee56059 (patch)
tree20de79c5f9db89542cc122f83c4d19fa8e6e926b
parentbce7b5e363957c134f944769e677354467b7e4ed (diff)
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Merge fesvr into spike repo; bump spike to v1.0.0
-rw-r--r--.gitmodules3
-rw-r--r--README.md2
-rwxr-xr-xbuild-rv32ima.sh3
-rwxr-xr-xbuild-spike-only.sh3
-rwxr-xr-xbuild-spike-pk.sh3
-rwxr-xr-xbuild.sh3
m---------riscv-fesvr0
m---------riscv-isa-sim0
8 files changed, 4 insertions, 13 deletions
diff --git a/.gitmodules b/.gitmodules
index 1c35ad9..1b3fc0a 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,9 +1,6 @@
[submodule "riscv-isa-sim"]
path = riscv-isa-sim
url = https://github.com/riscv/riscv-isa-sim.git
-[submodule "riscv-fesvr"]
- path = riscv-fesvr
- url = https://github.com/riscv/riscv-fesvr.git
[submodule "riscv-pk"]
path = riscv-pk
url = https://github.com/riscv/riscv-pk.git
diff --git a/README.md b/README.md
index 0e9ecb3..08ff1c1 100644
--- a/README.md
+++ b/README.md
@@ -13,8 +13,6 @@ enumeration of all RISC-V opcodes executable by the simulator
a boot loader for Linux and similar OS kernels, and `pk`, a proxy kernel that
services system calls for a target-machine application by forwarding them to
the host machine
-* [riscv-fesvr](https://github.com/riscv/riscv-fesvr/), the host side of
-a simulation tether that services system calls on behalf of a target machine
Several RISC-V tools that were previously maintained through this repository
have since been upstreamed to their parent projects. Although this repository
diff --git a/build-rv32ima.sh b/build-rv32ima.sh
index b094174..1f9a363 100755
--- a/build-rv32ima.sh
+++ b/build-rv32ima.sh
@@ -7,8 +7,7 @@
echo "Starting RISC-V Toolchain build process"
-build_project riscv-fesvr --prefix=$RISCV
-build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV --with-isa=rv32ima
+build_project riscv-isa-sim --prefix=$RISCV --with-isa=rv32ima
build_project riscv-gnu-toolchain --prefix=$RISCV --with-arch=rv32ima --with-abi=ilp32
CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv32-unknown-elf
build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --disable-werror
diff --git a/build-spike-only.sh b/build-spike-only.sh
index ac3fda5..e45a77d 100755
--- a/build-spike-only.sh
+++ b/build-spike-only.sh
@@ -6,7 +6,6 @@
echo "Starting RISC-V Toolchain build process"
-build_project riscv-fesvr --prefix=$RISCV
-build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV
+build_project riscv-isa-sim --prefix=$RISCV
echo -e "\\nRISC-V Toolchain installation completed!"
diff --git a/build-spike-pk.sh b/build-spike-pk.sh
index 02f3202..af08a69 100755
--- a/build-spike-pk.sh
+++ b/build-spike-pk.sh
@@ -13,8 +13,7 @@ fi
echo "Starting RISC-V Toolchain build process"
-build_project riscv-fesvr --prefix=$RISCV
-build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV
+build_project riscv-isa-sim --prefix=$RISCV
CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv64-unknown-elf
echo -e "\\nRISC-V Toolchain installation completed!"
diff --git a/build.sh b/build.sh
index 4fa357e..9aa80b6 100755
--- a/build.sh
+++ b/build.sh
@@ -18,8 +18,7 @@ check_version automake 1.14 "OpenOCD build"
check_version autoconf 2.64 "OpenOCD build"
build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror
-build_project riscv-fesvr --prefix=$RISCV
-build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV
+build_project riscv-isa-sim --prefix=$RISCV
build_project riscv-gnu-toolchain --prefix=$RISCV
CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv64-unknown-elf
build_project riscv-tests --prefix=$RISCV/riscv64-unknown-elf
diff --git a/riscv-fesvr b/riscv-fesvr
deleted file mode 160000
-Subproject 21e48156e8dc2d0ac53bee50c72b022f9552965
diff --git a/riscv-isa-sim b/riscv-isa-sim
-Subproject 5b08bf5c3cc236ed6baf6d4f2964d8efe5b1705
+Subproject 2710fe575e7e6a4e2418224f8d254d5ca31f6c0