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When cputchar was fixed for RV32, virtual memory was not taken into
consideration. If cputchar was called in supervisor mode, with virtual
memory enabled, the pointers given to the HTIF would have wrongfully
been virtual addresses.
Translate pointers to always be physical addresses to support cputchar
with both virtual memory enabled and disabled. Defined macro kaa2pa is
short for 'kernel any address to physical address'.
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Although, usually, caches for in-memory memory-management data
structures (e.g. TLB) are empty on reset, implicit references to such
data structures, due to instruction execution, might not necessarily be
ordered with respect to explicit writes. An SFENCE.VMA guarantees such
ordering.
This is necessary in order to ensure that when trapping into S mode the
hart sees the correct address translation mappings for supervisor level
code. For user level code, the supervisor already executes an SFENCE.VMA
when mapping the pages.
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As blocking character device is not supported in RV32,
use a proxy syscall to allow writing to the console.
Note that we have to wait for a response from the
device, since we would otherwise be freeing the pointer
sent to the device.
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The default RVTEST_VECTOR_ENABLE macro always write fcsr and cause tests
failure on vector processor without float support. This commit add new
macro to init only vector related register.
Signed-off-by: Avimitin <dev@avimit.in>
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This makes it easier to support tests with large memory footprints,
as the default 63 pages may be insufficient
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Enable RNMIs if the extension is present, as the feature affects trap
behavior when RNMIs are masked.
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Resolves https://github.com/riscv-software-src/riscv-tests/issues/460
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Certain tests (particularly negative) may require a fault to occur.
However in order to pass the tests, page fault and traps must return back
to the tests. This patch add support for page fault and trap filtering
in env.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
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In "evict" function in v/vm.c, when evict a dirty page in user space, memcpy should be from that page, rather than to evicted page.
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* update riscv_arch.h to support QEMU:
add size attribute for tohost/fromhost
add writing zero to (tohost + 4) to write_tohost
* revert the align of tohost/fromhost to 64 bytes
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See also https://github.com/riscv/riscv-pk/pull/240
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Minor clang-related fixes
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The RISC-V Privileged ISA v1.10 uses stval instead of
sbadaddr. Although GCC can cope with sbadaddr, clang cannot. It fails
with:
error: operand must be a valid system register name or an integer in
the range [0, 4095]
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The RISC-V Privileged ISA v1.10 uses satp instead of sptbr. Although
GCC can cope with sptbr, clang cannot. It fails with:
error: operand must be a valid system register name or an integer in
the range [0, 4095]
Modified the variable name in vm.c as well to ensure consistency and
avoid possible confusion.
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Unconditionally clear mie register while disabling interrupts.
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fix a building error
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riscv64-unknown-elf-gcc -march=rv32g -mabi=ilp32 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -DENTROPY=0xf7930f7 -std=gnu99 -O2 -I/data/riscv/riscv-tools/riscv-tests/isa/../env/v -I/data/riscv/riscv-tools/riscv-tests/isa/macros/scalar -T/data/riscv/riscv-tools/riscv-tests/isa/../env/v/link.ld /data/riscv/riscv-tools/riscv-tests/isa/../env/v/entry.S /data/riscv/riscv-tools/riscv-tests/isa/../env/v/*.c rv32ui/simple.S -o rv32ui-v-simple
/opt/riscv/lib/gcc/riscv64-unknown-elf/10.1.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/cc8oFAkO.o: in function `tohost':
(.tohost+0x0): multiple definition of `tohost'; /tmp/ccOTKaAa.o:(.sbss+0x10): first defined here
/opt/riscv/lib/gcc/riscv64-unknown-elf/10.1.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/cc8oFAkO.o: in function `fromhost':
(.tohost+0x40): multiple definition of `fromhost'; /tmp/ccOTKaAa.o:(.sbss+0x8): first defined here
collect2: error: ld returned 1 exit status
/data/riscv/riscv-tools/riscv-tests/isa/Makefile:74: recipe for target 'rv32ui-v-simple' failed
make[1]: *** [rv32ui-v-simple] Error 1
make[1]: Leaving directory '/data/riscv/riscv-tools/riscv-tests/isa'
Makefile:28: recipe for target 'isa' failed
make: *** [isa] Error 2
Signed-off-by: Zhi Yong Wu <zhiyong.wu@sophgo.com>
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Rvv 0.9
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1. add rtz rounding instructions
2. add vfslide instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Don't make assumptions about delegatability in medeleg.
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This isn't required for correctness, but it helps debugging (and, in a few
restricted scenarios, it avoids x-prop issues).
Closes #16
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Ecall and vector
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1. mstatus.vs is similar to mstatus.fs but desiged for vector extension.
2. add mstatus.vs initialization macro. The macro also enables floating unit.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Some simulators support semihosting feature to brigde syscall to host.
The change keep the exit syscall and the arguments in the related registers.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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This caused it to collapse to 0, preventing coherence_torture from doing
anything interesting at all...
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Inform GCC that "sfence.vma" clobbers memory
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