1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
|
# See LICENSE for license details.
#*****************************************************************************
# wakeup.S
#-----------------------------------------------------------------------------
#
# Test wakeup.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64UV
RVTEST_CODE_BEGIN
# make sure these don't choke at the beginning
fence
fence rw,io
fence io,rw
# this shouldn't go through since app vl is zero
la a3,src1
la a4,src2
vld vx2,a3
vld vx3,a4
lui a0,%hi(vtcode1)
vf %lo(vtcode1)(a0)
la a5,dest
vsd vx2,a5
fence
ld a1,0(a5)
li a2,0xdeadbeefcafebabe
li TESTNUM,2
bne a1,a2,fail
ld a1,8(a5)
li TESTNUM,3
bne a1,a2,fail
ld a1,16(a5)
li TESTNUM,4
bne a1,a2,fail
ld a1,24(a5)
li TESTNUM,5
bne a1,a2,fail
# check default hw vector length, which is 32
li a3, 32
vsetvl a3, a3
li a0, 32
li TESTNUM, 6
bne a3, a0, fail
li a3, 33
vsetvl a3, a3
li a0, 32
li TESTNUM, 7
bne a3, a0, fail
li a3, 31
vsetvl a3, a3
li a0, 31
li TESTNUM, 8
bne a3, a0, fail
# now do some vector stuff without vsetcfg
vsetvl x0, x0
li a3, 4
la a4,src1
la a5,src2
vsetvl a3, a3
vld vx2,a4
vld vx3,a5
lui a0,%hi(vtcode1)
vf %lo(vtcode1)(a0)
la a5,dest
vsd vx2,a5
fence
ld a1,0(a5)
li a2,5
li TESTNUM,9
bne a1,a2,fail
ld a1,8(a5)
li TESTNUM,10
bne a1,a2,fail
ld a1,16(a5)
li TESTNUM,11
bne a1,a2,fail
ld a1,24(a5)
li TESTNUM,12
bne a1,a2,fail
# initialize dest memory
li a3, 0xdeadbeefcafebabe
sd a3, 0(a5)
sd a3, 8(a5)
sd a3, 16(a5)
sd a3, 24(a5)
# test app vl zero again
li a3, 0
vsetvl a3, a3
la a3,src1
la a4,src2
vld vx2,a3
vld vx3,a4
lui a0,%hi(vtcode1)
vf %lo(vtcode1)(a0)
la a5,dest
vsd vx2,a5
fence
ld a1,0(a5)
li a2,0xdeadbeefcafebabe
li TESTNUM,13
bne a1,a2,fail
ld a1,8(a5)
li TESTNUM,14
bne a1,a2,fail
ld a1,16(a5)
li TESTNUM,15
bne a1,a2,fail
ld a1,24(a5)
li TESTNUM,16
bne a1,a2,fail
j pass
vtcode1:
add x2,x2,x3
stop
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
src1:
.dword 1
.dword 2
.dword 3
.dword 4
src2:
.dword 4
.dword 3
.dword 2
.dword 1
dest:
.dword 0xdeadbeefcafebabe
.dword 0xdeadbeefcafebabe
.dword 0xdeadbeefcafebabe
.dword 0xdeadbeefcafebabe
RVTEST_DATA_END
|