| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-10-19 | use registers present on rv32e (#299) | Sandeep Rajendran | 1 | -4/+4 |
| 2020-03-21 | Move self-modifying 'fence.i' ops to .data memory section (#269) | WRansohoff | 1 | -6/+14 |
| 2016-07-22 | Simplify fence.i test for RVC | Andrew Waterman | 1 | -10/+10 |
| 2016-07-11 | Remove instruction width assumptions to support RVC | Andrew Waterman | 1 | -0/+1 |
| 2015-01-09 | Add LICENSE | Andrew Waterman | 1 | -0/+2 |
| 2013-04-22 | initial commit | Yunsup Lee | 1 | -0/+51 |
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index : riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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