| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2021-05-12 | Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: (#... | SLAMET RIANTO | 1 | -0/+1 |
| 2021-05-10 | Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support C... | SLAMET RIANTO | 1 | -0/+7 |
| 2017-11-01 | SBREAK test now checks EPC value. (#92) | Christopher Celio | 1 | -0/+4 |
| 2017-10-30 | Declare trap handlers as global symbols. (#87) | Richard Xia | 1 | -0/+1 |
| 2016-07-11 | Remove instruction width assumptions to support RVC | Andrew Waterman | 1 | -6/+3 |
| 2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 1 | -0/+1 |
| 2015-03-25 | split out S-mode tests and M-mode tests | Yunsup Lee | 1 | -3/+8 |
| 2015-03-21 | Merge rv64si and rv32si tests | Andrew Waterman | 1 | -0/+43 |
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index : riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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