| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-03-21 | Make misa.C test conform to Hauser proposal | Andrew Waterman | 1 | -43/+10 |
| 2018-02-27 | Add test for clearing misa.C while PC is misaligned (#117) | Andrew Waterman | 1 | -1/+79 |
| 2017-11-11 | Make sure that code is 4-byte aligned before disabling rvc (#100) | Andrew Waterman | 1 | -0/+1 |
| 2017-10-30 | Declare trap handlers as global symbols. (#87) | Richard Xia | 1 | -0/+1 |
| 2017-10-26 | Verify that mtval/stval is written correctly on misaligned fetch | Andrew Waterman | 1 | -1/+9 |
| 2017-09-01 | Improve ma_fetch test to cover JAL and branches | Andrew Waterman | 1 | -1/+48 |
| 2016-07-22 | Make ma_fetch test robust against code size changes | Andrew Waterman | 1 | -2/+4 |
| 2016-07-11 | Remove instruction width assumptions to support RVC | Andrew Waterman | 1 | -0/+1 |
| 2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 1 | -0/+1 |
| 2016-03-03 | Fix ma_fetch to work with or without RVC | Andrew Waterman | 1 | -8/+18 |
| 2015-03-25 | split out S-mode tests and M-mode tests | Yunsup Lee | 1 | -3/+8 |
| 2015-03-21 | Merge rv64si and rv32si tests | Andrew Waterman | 1 | -0/+83 |
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index : riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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