| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2015-07-05 | New M-mode timers | Andrew Waterman | 2 | -8/+0 |
| 2015-04-03 | Run RV32 tests on spike with --isa=RV32 | Andrew Waterman | 2 | -2/+4 |
| 2015-03-25 | split out S-mode tests and M-mode tests | Yunsup Lee | 2 | -13/+0 |
| 2015-03-21 | Merge rv64si and rv32si tests | Andrew Waterman | 8 | -286/+15 |
| 2015-03-17 | Merge [shm]call into ecall, [shm]ret into eret | Andrew Waterman | 1 | -1/+1 |
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 8 | -84/+43 |
| 2015-02-19 | Unify rv32/rv64 timer tests | Andrew Waterman | 1 | -38/+3 |
| 2015-01-09 | Add LICENSE | Andrew Waterman | 10 | -0/+20 |
| 2015-01-02 | On misaligned fetch, EPC = branch target, not source | Andrew Waterman | 1 | -5/+8 |
| 2014-11-22 | relax rv32si timer test a bit | Yunsup Lee | 1 | -1/+2 |
| 2014-11-13 | remove zscale specific tests | Yunsup Lee | 4 | -192/+0 |
| 2014-11-13 | make rv32si fault load/store test stronger | Yunsup Lee | 1 | -1/+5 |
| 2014-11-12 | beef up rv32si tests | Yunsup Lee | 11 | -0/+547 |
| 2014-01-31 | Add rv32si tests, including illegality of shamt[5] | Andrew Waterman | 4 | -0/+87 |
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index : riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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