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AgeCommit message (Expand)AuthorFilesLines
2022-12-07zicntr: separate cycle/instret accessibility test (#439)Chih-Min Chao2-2/+11
2022-06-09Test misaligned stores. (#397)Tim Newsome3-0/+18
2022-06-07Test misaligned loads.Tim Newsome3-0/+18
2022-06-07Set TESTNUM before executing code.Tim Newsome1-2/+1
2021-02-01Align mtvec in rv32mi-p-shamt testAndrew Waterman1-0/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman1-2/+0
2020-03-18Fix shamt.S header (#264)Takahiro1-2/+2
2018-08-17making mtvec_handler global (#150)Srivatsa Yogendra1-0/+1
2017-05-17Manually assemble bad shift amount, since assembler rejectsAndrew Waterman1-1/+1
2017-04-07Remove defunct IPI testsAndrew Waterman2-10/+0
2016-07-29Add RV32 RVC and breakpoint testsAndrew Waterman2-1/+10
2016-07-22Move rv32mi dirty bit test to rv32siAndrew Waterman2-11/+0
2016-07-07Update WFI test for priv v1.9Andrew Waterman2-9/+0
2016-04-30ERET -> xRET; new memory mapAndrew Waterman2-10/+1
2016-03-10Add missing rv32mi/rv32si testsAndrew Waterman4-0/+28
2016-03-03Some S-mode tests really only belong in M-modeAndrew Waterman4-8/+50
2015-07-05New M-mode timersAndrew Waterman1-4/+3
2015-04-03Run RV32 tests on spike with --isa=RV32Andrew Waterman1-0/+2
2015-03-25split out S-mode tests and M-mode testsYunsup Lee9-0/+81
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