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Test that we work correctly when the hart we're debugging ceases to
respond while it's running.
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Test that we work correctly when the hart we're debugging ceases to
respond during stepi.
Add wait parameter to Gdb.stepi(), in case stepi isn't expected to complete.
Parse "could not read registers" error from gdb
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Confirm basic debug still works when other harts have been parked using
a `cease` instruction. Check that the unavailable harts are inaccessible
from gdb.
Add Gdb.expect()
Parse "unknown thread" error from gdb.
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Also make the semi-hosting test program return 10. That's more fragile
than returning 0, so makes for a better test.
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This gives you less noise in the log, and more chance of figuring out
what code was actually executed.
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`flush regs` is being deprecated.
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`cease` is not a standard RISC-V extension, but is (was?) implemented in
Rocket, and also exists in some SiFive cores. It's useful to test
OpenOCD behavior when a hart becomes unavailable.
See also https://github.com/chipsalliance/rocket-chip/issues/1868
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Also change the test itself to require less RAM than it did previously.
(It had required more than 32KB.)
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It would fail intermittently. We can't guarantee all harts resume
simultaneously. When we let multiple harts run to a breakpoint at the
end of the same loop, one is likely to get there first, and the second
won't make it.
To avoid this problem, run for a short amount of time instead of to a
breakpoint.
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Before it might fail incorrectly, because main was close to trap_entry.
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* Specify trigger type=2 in trigger.S
Previous tests implicitly assume triggers only support type=2. However,
a trigger may support multiple types, i.e., type=15. This commit
explicitly specifies type=2 in trigger.S to support type 15.
* Update debug/programs/trigger.S
Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
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Between October 13 and October 19, something happened that makes the
multi-spike tests 4 times slower. Rolling back spike, OpenOCD, or
riscv-tests doesn't affect this. Presumably it's due to a kernel or
python change in my Ubuntu system.
I don't have time to look at this right now, so just increase the timeouts. :-(
If I had to guess, there could be a bug in rbb_daisychain.py that wastes
a lot of time.
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https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART
at the address we were using in our 32-bit debug tests.
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Fix long line to make pylint happy.
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Using the new spike support merged in
https://github.com/riscv-software-src/riscv-isa-sim/pull/1109
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Not as useful as I'd like because we don't connect until after examine()
has completed, and the test is likely to time out while debugging. But
good to have, and maybe I'll expand on it one day.
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update gdbserver.py; tolerance value of MemorySampleTest()
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The control sequences (^[[?2004h and ^[[?2004l) occur after the
gdb.command, which results in Exception fault. This commit removes the
control sequences and strips out the blank lines (^M).
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These can change at any time and that is OK.
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I don't have time to fix the bug right now, and nobody has run into the
bug yet in any case.
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Turn semihosting_fileio on for every hart. This test still fails if it
ends up running on hart 1 instead of 0, but at least it's closer to
passing. Feels like the remaining problem is in OpenOCD.
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* Another pylint upgrade.
Lots of format string changes, which are more readable.
More files to come...
* Satisfy pylint for two more files.
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In the original test, confirm that stdout data ends up in the OpenOCD
log.
In the new test, with `arm semihosting_fileio` enabled, confirm that
stdout data ends up in gdb's CLI.
This test requires https://github.com/riscv/riscv-openocd/pull/699.
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I'm running a newer version of pylint, and thus there are new warnings
to be fixed. All very minor.
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regions (#388)
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Adjust test to work with that.
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* Add EbreakTest.
Confirm correct behavior when somebody bakes an ebreak instruction into
their code.
* Forgot to commit ebreak.c
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That way it can go into flash.
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It includes the name in quotes:
```* 2 Thread 1 "Current Execution" (Name: Current Execution) 0x10000100 in main```
Just ignore that part.
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Now it will give slightly more helpful output if it fails.
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(#369)
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This feature lets you easily interact with the gdb after the test has
run to a certain point.
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They used to set U, A, D, in intermediate page table entries which is no
longer allowed.
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The tests don't confirm that the order actually changes, but at least
the code that does the work now is executed during the tests.
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Disconnects from gdb, and then reconnects, making sure that didn't
change any of the registers.
This test will start passing when
https://github.com/riscv/riscv-openocd/pull/661 merges.
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Useful for estimating interactive performance.
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It's not an argument to spike anymore.
Also switch testing the vector unit from multi-gdb to `-rtos hwthread`.
This exposes a bug in OpenOCD (which is already fixed).
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1. Don't run all tests in multi-spike. Extra coverage is negligible, and
it just takes too long.
2. Increase a few timeouts.
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* Test debugging multiple spikes in a daisy chain.
* Hugely speed up rbb_daisychain.
Now 2 dual-hart spikes are less than 4x slower than a single dual-hart
spike.
* WIP
* Test daisy chained homogeneous spike instances.
For OpenOCD, this means we're checking that we can talk to multiple
TAPs. Next up is heterogeneous testing.
* Enable Sv48Test.
Didn't mean to disable it with this commit.
* Test authentication again.
Another change I hadn't meant to push...
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* Add FreeRTOS smoke tests.
Make sure that OpenOCD can access all threads in a FreeRTOS binary on
single-hart RV32 and RV64.
* Also test `-rtos FreeRTOS`.
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