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Age
Commit message (
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Author
Files
Lines
2022-05-16
V implies FD now. (#382)
Tim Newsome
1
-3
/
+3
2021-11-12
Set `riscv resume_order reversed`. (#363)
Tim Newsome
1
-0
/
+2
2021-10-05
Remove slen. (#360)
Tim Newsome
3
-18
/
+14
2021-05-20
Test multiple heterogeneous spike instances. (#338)
Tim Newsome
3
-22
/
+9
2021-05-07
Test daisy chained homogeneous spike instances. (#334)
Tim Newsome
4
-2
/
+89
2021-04-13
Add FreeRTOS smoke tests. (#333)
Tim Newsome
3
-4
/
+9
2021-01-25
Smoketest that vl and vtype can be modified. (#320)
Tim Newsome
1
-29
/
+0
2021-01-07
Stop testing `-rtos riscv`. (#314)
Tim Newsome
1
-20
/
+0
2020-12-31
Make HiFiveUnleashed tests clean.
Tim Newsome
5
-0
/
+9
2020-12-14
Add tests for memory sampling feature. (#300)
Tim Newsome
6
-0
/
+6
2020-10-08
Expose registers on all harts in openocd cfgs (#297)
Samuel Obuch
2
-4
/
+10
2020-08-06
Add enable_rtos_riscv (#288)
Tim Newsome
1
-0
/
+2
2020-06-25
Add manual hwbp test. (#283)
Tim Newsome
2
-0
/
+2
2020-05-26
Test semihosting calls (#280)
Tim Newsome
5
-5
/
+14
2020-04-10
Change slen to a value that spike supports. (#271)
Tim Newsome
1
-1
/
+3
2020-03-18
Specify misa for HiFive Unleashed. (#259)
Tim Newsome
1
-0
/
+2
2020-02-14
Add tests for vector register access (#244)
Tim Newsome
3
-10
/
+13
2019-12-18
Hardcode misa values for all spike targets. (#227)
Tim Newsome
8
-7
/
+19
2019-12-02
Use a small binary to set up HiFive Unleashed. (#221)
Tim Newsome
3
-10
/
+10
2019-10-15
Add support to run all tests against HiFive Unleashed. (#212)
Tim Newsome
5
-0
/
+184
2019-10-09
Remove ocd_ prefix. (#210)
Tim Newsome
4
-4
/
+4
2019-08-02
Miscellaneous minor test improvements (#199)
Tim Newsome
1
-1
/
+3
2019-07-15
Use work area in spike-1 to cover CRC algorithm. (#195)
Tim Newsome
1
-0
/
+2
2019-05-16
Cover with/without halt groups. (#191)
Tim Newsome
4
-5
/
+6
2019-04-08
Test lack of abstract CSR access. (#187)
Tim Newsome
6
-6
/
+9
2019-04-04
Test simultaneous resume using hasel. (#186)
Tim Newsome
4
-5
/
+11
2019-02-14
Test `-rtos hwthread` (#178)
Tim Newsome
3
-0
/
+57
2018-12-31
Add testing of run-test/idle cases.
Tim Newsome
6
-6
/
+7
2018-11-14
Merge pull request #165 from riscv/flash
Tim Newsome
2
-0
/
+59
2018-11-14
Cleanup and renamed test flag to invalid_memory_returns_zero
cgsfv
2
-2
/
+2
2018-11-13
Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix
cgsfv
2
-2
/
+4
2018-10-31
Add HiFive1-flash target configuration.
Tim Newsome
2
-0
/
+59
2018-09-13
Assert if HiFive1 program is too large.
Tim Newsome
1
-0
/
+2
2018-08-29
Add test case for `riscv expose_custom`.
Tim Newsome
9
-0
/
+9
2018-04-19
Delete E300Sim.py
debug-delete-sim
Megan Wachs
1
-17
/
+0
2018-04-02
Use `gdb_report_register_access_error enable`
Tim Newsome
4
-0
/
+6
2018-03-27
Test debug authentication.
Tim Newsome
3
-3
/
+18
2018-03-01
Test debugging with/without a program buffer
Tim Newsome
3
-3
/
+3
2018-03-01
Ensure an error when reading a non-existent CSR.
Tim Newsome
4
-0
/
+16
2018-02-07
Link scripts shouldn't be executable.
Tim Newsome
1
-0
/
+0
2017-12-27
Test FPRs that aren't XLEN in size.
Tim Newsome
4
-4
/
+6
2017-10-24
Increase dual-core RV64 timeouts.
Tim Newsome
2
-2
/
+2
2017-09-29
Fix tests to work in multi-gdb mode.
Tim Newsome
9
-4
/
+48
2017-09-21
Add coverage for single-core non-rtos OpenOCD.
Tim Newsome
4
-3
/
+19
2017-09-19
Allow multiple reset vectors.
Tim Newsome
2
-2
/
+2
2017-09-01
Use 32-bit link script for 32-bit target.
Tim Newsome
1
-1
/
+1
2017-08-28
This file isn't ready yet.
Tim Newsome
1
-11
/
+0
2017-08-28
Increase remotetimeout for spike targets.
Tim Newsome
5
-0
/
+15
2017-08-28
Make pylint happy.
Tim Newsome
3
-3
/
+3
2017-08-28
WIP multicore testing.
Tim Newsome
4
-0
/
+8
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