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path: root/debug/targets.py
AgeCommit message (Expand)AuthorFilesLines
2023-10-24Support instruction count limit in IcountTestliangzhen1-0/+3
2023-10-17Merge pull request #513 from lz-bro/nonexist_csrTim Newsome1-0/+3
2023-10-17Make the non-existent csr configurableliangzhen1-0/+3
2023-10-16Make CLINT address configurableliangzhen1-1/+5
2023-07-17debug: Add support_unavailable_control property.Tim Newsome1-0/+3
2023-06-30Fix for https://github.com/riscv-software-src/riscv-tests/issues/482Tommy Murphy1-2/+2
2023-05-25debug: New pylint => new warnings => new cleanupsTim Newsome1-1/+4
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome1-0/+3
2022-10-07debug: Add --debug_server arg to open gdb on OpenOCDTim Newsome1-1/+5
2022-06-23Another pylint upgrade. (#398)Tim Newsome1-20/+21
2022-05-31Address pylint warnings. (#385)Tim Newsome1-0/+1
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome1-9/+16
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome1-0/+7
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome1-2/+7
2021-01-08Disable V extension when compiler doesn't support it. (#317)Tim Newsome1-2/+24
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome1-0/+4
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome1-0/+4
2020-06-25Add manual hwbp test. (#283)Tim Newsome1-0/+4
2020-06-25Create a more sophisticated vector test (#284)Tim Newsome1-1/+1
2020-05-26Test semihosting calls (#280)Tim Newsome1-0/+4
2020-03-05Add a simple mechanism to skip tests on targets. (#251)Tim Newsome1-0/+7
2019-11-22Move to Python 3. (#218)Tim Newsome1-3/+2
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-2/+1
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome1-15/+27
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome1-0/+3
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv1-2/+2
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv1-0/+3
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome1-0/+4
2017-11-19Make pylint happy.Tim Newsome1-9/+11
2017-11-17debug: Fix the XLEN command line checkxlen_fixMegan Wachs1-7/+8
2017-11-16Debug: Use the --32 and --64 command line arguments (#97)Megan Wachs1-0/+5
2017-11-01Make pylint 1.6.5 happy.Tim Newsome1-1/+1
2017-10-12Pay attention to server_timeout_secTim Newsome1-2/+3
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome1-0/+2
2017-09-19Allow multiple reset vectors.Tim Newsome1-0/+5
2017-09-14Test debugging code with interrupts.Tim Newsome1-0/+3
2017-09-01Add some infrastructure for multicore tests.Tim Newsome1-29/+28
2017-08-28Make the debug tests aware of multicore.Tim Newsome1-61/+83
2017-08-14Put logfile code back so everything works again.Tim Newsome1-2/+2
2017-08-14debug: Allow OpenOCD startup timeout to be specified. Print out path to log f...Megan Wachs1-1/+8
2017-07-20Add back code to clean up triggers in entry.STim Newsome1-0/+6
2017-07-03Add gdb_setup to target for arbitrary gdb commandsTim Newsome1-0/+4
2017-06-26Move target definition into individual files.Tim Newsome1-111/+74
2017-06-15Test 64-bit addressing.Tim Newsome1-7/+17
2017-06-05Make pylint happy.Tim Newsome1-1/+2
2017-05-18debug: Correct the calling for a 32-bit simulation targetMegan Wachs1-1/+1
2017-05-16Change Spike's RAM location to match the linker scriptPalmer Dabbelt1-2/+2
2017-05-15debug: Use consistent 'sim_cmd' argument.Megan Wachs1-1/+1
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops (...Megan Wachs1-2/+2
2017-04-17debug: Checkpoint restoring Spike functionalityMegan Wachs1-11/+11
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