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2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome1-0/+2
Also make the semi-hosting test program return 10. That's more fragile than returning 0, so makes for a better test.
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome1-0/+12
`cease` is not a standard RISC-V extension, but is (was?) implemented in Rocket, and also exists in some SiFive cores. It's useful to test OpenOCD behavior when a hart becomes unavailable. See also https://github.com/chipsalliance/rocket-chip/issues/1868
2022-12-01Share exit() among more tests. (#433)Tim Newsome1-1/+1
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome1-1/+1
Also change the test itself to require less RAM than it did previously. (It had required more than 32KB.)
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome1-1/+1
It would fail intermittently. We can't guarantee all harts resume simultaneously. When we let multiple harts run to a breakpoint at the end of the same loop, one is likely to get there first, and the second won't make it. To avoid this problem, run for a short amount of time instead of to a breakpoint.
2022-10-26Specify trigger type=2 in trigger.S (#425)YenHaoChen1-2/+3
* Specify trigger type=2 in trigger.S Previous tests implicitly assume triggers only support type=2. However, a trigger may support multiple types, i.e., type=15. This commit explicitly specifies type=2 in trigger.S to support type 15. * Update debug/programs/trigger.S Co-authored-by: Tim Newsome <tim@sifive.com> Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> Co-authored-by: Tim Newsome <tim@sifive.com>
2022-06-08Test semihosting_fileioTim Newsome1-1/+3
In the original test, confirm that stdout data ends up in the OpenOCD log. In the new test, with `arm semihosting_fileio` enabled, confirm that stdout data ends up in gdb's CLI. This test requires https://github.com/riscv/riscv-openocd/pull/699.
2022-04-25Add EbreakTest. (#380)Tim Newsome1-0/+31
* Add EbreakTest. Confirm correct behavior when somebody bakes an ebreak instruction into their code. * Forgot to commit ebreak.c
2021-11-29Fix TranslateTests. (#365)Tim Newsome1-3/+5
They used to set U, A, D, in intermediate page table entries which is no longer allowed.
2021-07-19Debug tests: catch write to nonexistent trigger registers in entry.S (#348)Luke Wren1-0/+7
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome1-0/+2
2020-06-25Create a more sophisticated vector test (#284)Tim Newsome1-0/+159
* WIP * WIP * Vector test seems to work well with spike. * Check a0 in case the program didn't work right. * Return not applicable if compile doesn't support V
2020-05-26Test semihosting calls (#280)Tim Newsome2-0/+155
* Add a basic semihosting test. * Need to configure semihosting on each target. * WIP * Parse "cannot insert breakpoint" message. Also use sys.exit instead of exit, per new pylint's suggestion.
2020-03-26Improve address translation tests (#261)Tim Newsome1-4/+16
* Improve address translation tests. Check that the mode we're testing is supported by hardware before running the test. Test with high address bits set, which catches a bug in OpenOCD. * Turn off PMP for address translation test. Otherwise it doesn't pass on HiFive Unleashed. * Run TranslateTest on random hart. Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work.
2020-02-11Generate very different values on different harts. (#238)Tim Newsome1-0/+1
This way if you end up reading a value that you suspect might be coming from another hart/register, you can clearly see where it came from.
2020-01-09Smoke test virtual address translation support. (#233)Tim Newsome5-13/+182
* WIP * Smoke test virtual address support. Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as large as possible pages to 1:1 map the rest of RAM so those sizes do get minimal coverage as well.
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome2-4/+13
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome2-17/+18
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2019-03-11Add SmpSimultaneousRunHalt test. (#181)Tim Newsome1-0/+17
This test confirms that in SMP configurations OpenOCD halts the harts near-simulatenously. (It'll also check for resume, but that's not implemented yet so commented out for now.)
2018-11-12Simpler/more idiomatic way to keep string on stackTim Newsome1-4/+1
2018-10-29Almost all tests pass with HiFive1-flashTim Newsome1-1/+1
Only TriggerDmode still fails.
2018-10-29Tweak debug tests to run out of flash.Tim Newsome2-1/+5
Not all tests pass when run out of flash yet, but it's getting a lot closer. The ones still failing on HiFive1-flash are: DebugSymbols, Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and TriggerStoreAddressInstant.
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome1-1/+1
Also tiny cleanups, making pylint happy.
2018-10-03Added tests for hw and sw watchpointscgsfv1-0/+17
2018-09-13Put debug test stack in data instead of textTim Newsome1-0/+1
2018-04-27debug: add missing align directive on trap_entrytrap_entry_align-1Megan Wachs1-0/+1
2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome1-10/+3
2017-11-27Rename sbadaddr to satpAndrew Waterman1-3/+3
2017-09-19Merge pull request #76 from riscv/multicoreTim Newsome2-13/+20
Add interrupts to MulticoreRunHaltStepiTest.
2017-09-19Forgot to commit this earlier.Tim Newsome1-0/+20
Fixes #77.
2017-09-18Add interrupts to MulticoreRunHaltStepiTest.Tim Newsome2-13/+20
Just to hammer on anything at once, and hopefully catch weird interactions if they exist.
2017-09-14Test debugging code with interrupts.Tim Newsome3-4/+34
2017-09-01Add some infrastructure for multicore tests.Tim Newsome2-8/+30
When compiling, define the number of harts. This means we only need to allocate a lot of stack if there are a lot of harts.
2017-08-28Forgot to add this file.Tim Newsome1-0/+81
2017-08-28WIP multicore testing.Tim Newsome1-7/+36
2017-08-28Make the debug tests aware of multicore.Tim Newsome2-12/+7
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-07-20Add back code to clean up triggers in entry.STim Newsome1-0/+9
Then for targets that can't handle this because they don't implement hmode, add a target setting that allows that to be specified.
2017-07-03Don't clear triggers during execution.Tim Newsome1-9/+0
This shouldn't affect triggers set by the debugger, because running code can't change those. When it does affect them, it breaks Hwbp1 which sets the breakpoint before running the program.
2017-06-27Tolerate missing misa register.Tim Newsome1-1/+7
At least in the test programs. There are other places where this causes trouble as well.
2017-06-22Add basic multicore test.Tim Newsome1-33/+36
2017-06-20Smoketest multicore.Tim Newsome2-9/+40
When connecting to gdb, select a random thread and use that for the current test. Also replace infinite_loop with something that will later allow smoketesting of more than one thread.
2017-06-15Test 64-bit addressing.Tim Newsome2-9/+4
The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000. Also a minor change to log file naming so that 'make all' works again. I'll fix this better later.
2017-05-16Link the infinate loop at 0x10000000Palmer Dabbelt1-0/+0
Spike appears to have a problem geterating DTS at 0x80000000.
2017-05-16Link in encoding.h instead of providing a path to itPalmer Dabbelt5-4/+5
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops ↵Megan Wachs2-0/+14
(actually it just gets an exception anyway).
2017-04-14debug: checkpoint of trying to get simulation tests workingMegan Wachs2-2/+17
2017-03-29Prohibit relaxing the initial gp generationPalmer Dabbelt1-0/+3
I've added an additional linker relaxation that relaxes two instruction pc-relative sequences to one instruction gp relative sequences when possible. This sequence now optimizes the initial gp generation to mv gp, gp which is obviously bogus. The fix is to disable relaxations when setting up gp, preventing the linker from relaxing away this setup code.
2017-03-29Change the global pointer symbol to __global_pointer$Palmer Dabbelt1-1/+1
This changed a while ago in binutils.
2016-12-27Use compressed code if the target supports it.Tim Newsome2-2/+7
The main change was to read misa before running any other test. If misa indicates C is supported, then use compressed code. This required changing some tests, mostly to ensure correct alignment. The single step test also needs to know the correct addresses to step through in compressed code. Only print at most 1000 lines from each log file.
2016-12-07Use XLEN macro for these sources as well.Tim Newsome3-4/+4
All tests pass on spike32 and spike64 again.
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