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| author | Megan Wachs <megan@sifive.com> | 2017-04-14 10:24:32 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-04-14 10:24:32 -0700 |
| commit | 584af13876fc0a9d2225df376059b627ed5e56d7 (patch) | |
| tree | 19f428d46d2c741a8bda0b5e89ecfc54f1340db5 /debug/programs | |
| parent | 69b1dda5d9b184ff39d4e9c134f66a5bfe5bcef6 (diff) | |
| download | riscv-tests-584af13876fc0a9d2225df376059b627ed5e56d7.zip riscv-tests-584af13876fc0a9d2225df376059b627ed5e56d7.tar.gz riscv-tests-584af13876fc0a9d2225df376059b627ed5e56d7.tar.bz2 | |
debug: checkpoint of trying to get simulation tests working
Diffstat (limited to 'debug/programs')
| -rwxr-xr-x | debug/programs/entry.S | 15 | ||||
| -rw-r--r-- | debug/programs/mprv.S | 4 |
2 files changed, 17 insertions, 2 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index e021860..c9e319c 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -30,8 +30,23 @@ handle_reset: la t0, trap_entry csrw mtvec, t0 csrwi mstatus, 0 + + // make sure these registers exist by seeing if either S or U bits + // are set before attempting to zero them out. + csrr t1, misa + addi t2, x0, 1 + slli t2, t2, 20 // U_EXTENSION + and t2, t1, t2 + bne x0, t2, 1f + addi t2, x0, 1 + slli t2, t2, 18 // S_EXTENSION + and t2, t1, t2 + bne x0, t2, 1f + j 2f +1: csrwi mideleg, 0 csrwi medeleg, 0 +2: csrwi mie, 0 # initialize global pointer diff --git a/debug/programs/mprv.S b/debug/programs/mprv.S index 574f32e..cc1ca54 100644 --- a/debug/programs/mprv.S +++ b/debug/programs/mprv.S @@ -13,9 +13,9 @@ main: # update mstatus csrr t1, CSR_MSTATUS #if XLEN == 32 - li t0, (MSTATUS_MPRV | (VM_SV32 << 24)) + li t0, (MSTATUS_MPRV | (SPTBR_MODE_SV32 << 24)) #else - li t0, (MSTATUS_MPRV | (VM_SV39 << 24)) + li t0, (MSTATUS_MPRV | (SPTBR_MODE_SV39 << 24)) #endif #li t0, ((VM_SV39 << 24)) or t1, t0, t1 |