riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-09-13	Put debug test stack in data instead of text	Tim Newsome	1	-0/+1
2018-04-27	debug: add missing align directive on trap_entrytrap_entry_align-1	Megan Wachs	1	-0/+1
2017-09-18	Add interrupts to MulticoreRunHaltStepiTest.	Tim Newsome	1	-1/+1
2017-09-14	Test debugging code with interrupts.	Tim Newsome	1	-3/+1
2017-09-01	Add some infrastructure for multicore tests.	Tim Newsome	1	-8/+7
2017-08-28	WIP multicore testing.	Tim Newsome	1	-7/+36
2017-08-28	Make the debug tests aware of multicore.	Tim Newsome	1	-0/+7
2017-07-20	Add back code to clean up triggers in entry.S	Tim Newsome	1	-0/+9
2017-07-03	Don't clear triggers during execution.	Tim Newsome	1	-9/+0
2017-06-27	Tolerate missing misa register.	Tim Newsome	1	-1/+7
2017-04-14	debug: checkpoint of trying to get simulation tests working	Megan Wachs	1	-0/+15
2017-03-29	Prohibit relaxing the initial gp generation	Palmer Dabbelt	1	-0/+3
2017-03-29	Change the global pointer symbol to __global_pointer$	Palmer Dabbelt	1	-1/+1
2016-12-07	Use XLEN macro for these sources as well.	Tim Newsome	1	-1/+1
2016-12-06	avoid non-standard predefined macros	Andrew Waterman	1	-1/+1
2016-09-29	Clear triggers during entry.	Tim Newsome	1	-0/+9
2016-07-19	I think I've finally got malloc working right.	Tim Newsome	1	-3/+3
2016-07-18	Add block test.	Tim Newsome	1	-1/+1
2016-07-18	All tests pass with spike now.	Tim Newsome	1	-0/+132