index
:
riscv-tests.git
attempt-travis-fix
ceasetest2
compliance_tests
cs152-sp18-lab3
debug
debug-0.13
debug-clear-satp
debug-delete-sim
debug_auth
debug_disassemble
disable_unavailable
dma-memcpy
eos20-bringup
hw_watchpoint
interrupts
master
misc
no_progbuf
priv
privchange-dontdeleteme
python3
rekall
resume_from_trigger
riscv-tests-sail
rtos
rvt-master
smi-demo
split-isa-tests
sqrt-171
tmp
trap_entry_align
trap_entry_align-1
travis-dev
trigger_priority
usb_error
xlen_fix
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
benchmarks
/
common
/
util.h
Age
Commit message (
Expand
)
Author
Files
Lines
2023-05-22
Add vec-sgemm
Jerry Zhao
1
-0
/
+16
2017-03-22
Clean up benchmarks build
Andrew Waterman
1
-0
/
+5
2017-03-21
Remove smips/host-debugging cruft
Andrew Waterman
1
-50
/
+0
2016-07-07
Don't use FPU in benchmarks that don't need to use the FPU
Andrew Waterman
1
-2
/
+0
2016-03-14
Rework benchmarks to run in M-mode
Andrew Waterman
1
-2
/
+2
2015-01-09
Add LICENSE
Andrew Waterman
1
-0
/
+2
2014-12-12
Add more entropy to matrix multiplication input
Andrew Waterman
1
-0
/
+8
2014-11-07
Clean up canonical mt benchmarks and reorganize extra versions in /mt. All ve...
Henry Cook
1
-0
/
+11
2014-04-14
commit high-performance mm (scalar and vector versions)
Yunsup Lee
1
-5
/
+3
2014-04-07
Add radix sort benchmark
Andrew Waterman
1
-0
/
+2
2014-04-03
setStats in benchmarks now should set and unset the stats register. Also, rem...
Stephen Twigg
1
-4
/
+0
2014-03-25
Make qsort benchmark more meaningful
Andrew Waterman
1
-2
/
+2
2014-02-06
Clean up benchmarks; support uarch-specific counters
Andrew Waterman
1
-34
/
+94
2013-11-25
Update benchmarks to new privileged ISA
Andrew Waterman
1
-1
/
+1
2013-10-10
Benchmarks now run in user-mode.
Christopher Celio
1
-1
/
+29
2013-04-29
benchmarks initial commit
Yunsup Lee
1
-0
/
+32