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2014-02-04Add Stephen's vector FFT codeQuan Nguyen17-1/+1164
2014-02-03Add vfmsv instruction test, change vsetprec to vsetucfgQuan Nguyen3-2/+58
2014-01-31Shrink hex dumpsAndrew Waterman27-28/+2
2014-01-31Add rv32si tests, including illegality of shamt[5]Andrew Waterman8-15/+95
2014-01-31Minor Makefile improvementsHenry Cook2-3/+3
2014-01-31Make CSR test much more robustAndrew Waterman1-0/+52
2014-01-31Reference TESTNUM instead of x28 directlyAndrew Waterman69-217/+217
2014-01-23Done with rv32ui asm test portsEric Love1-2/+2
2014-01-23Fixed srl, srliEric Love3-25/+35
2014-01-23srl and sraiEric Love3-33/+33
2014-01-23First round of rv32ui asm testsEric Love50-15/+3410
2014-01-21Add CSRRx/CSRRxI testAndrew Waterman3-1/+35
2014-01-20Add packed vvadd test for confprec HwachaQuan Nguyen2-0/+106
2014-01-20Push envQuan Nguyen1-5/+5
2014-01-16Make LR/SC test more thoroughAndrew Waterman2-24/+37
2014-01-13Update v envAndrew Waterman1-5/+5
2013-11-28Fix load offsets for the vvadd_fw testAlbert Ou1-3/+3
2013-11-25Update benchmarks to new privileged ISAAndrew Waterman9-164/+38
2013-11-24Update to new privileged ISAAndrew Waterman17-88/+95
2013-11-19Add rv64uv-p-amoxor_{w,d} testsQuan Nguyen3-2/+118
2013-11-19fix rv64uv/vvadd_fd test to correctly check resultsYunsup Lee1-2/+2
2013-11-13added riscv-test-env as a submoduleYunsup Lee2-0/+8
2013-11-13split out envs from riscv-testsYunsup Lee12-1200/+0
2013-11-05add accelerator disabled causeYunsup Lee1-0/+1
2013-11-05correctly set SR_EA bit for all vector physical supervisor testsYunsup Lee12-0/+14
2013-11-05correctly set SR_EA bit for all vector physical testsYunsup Lee61-61/+64
2013-10-18revamp pt tests as wellYunsup Lee7-40/+31
2013-10-18hwacha virtual tests workingYunsup Lee7-44/+86
2013-10-17add hwacha exception supportYunsup Lee20-122/+448
2013-10-17disable vector bank testsYunsup Lee3-594/+594
2013-10-17add passing physical vector tests back inYunsup Lee4-5/+4
2013-10-17update out-of-date floating-point test in rv64uvYunsup Lee1-1/+1
2013-10-17fix broken amoor_w rv64uv testYunsup Lee1-0/+3
2013-10-10Merge branch 'master' of github.com:ucb-bar/riscv-testsChristopher Celio69-1837/+1795
2013-10-10Benchmarks now run in user-mode.Christopher Celio10-114/+104
- Jump to main performed by eret. - Nano trap handler added. - FinishTest refactored to perform SYS_exit, placed in util.h. - Only SYS_exit with test_result=1 results in a passed test. - Any other exceptions/syscalls/test_results end program with FAILED test. - PCR status set to S64/U64 if compiled in 64b.
2013-10-10revamp hwacha testsYunsup Lee69-1837/+1795
2013-09-21Re-enable virtual memory testsAndrew Waterman3-8/+15
2013-09-21New AUIPC semanticsAndrew Waterman1-6/+12
2013-09-15Don't emit vector instructions for nowAndrew Waterman2-0/+4
2013-09-11Add AMOXOR testAndrew Waterman3-2/+128
2013-08-25Don't build vector benchmarks for nowAndrew Waterman1-3/+3
2013-08-24don't emit vvcfg for nowAndrew Waterman2-3/+3
2013-08-23Add autoconf-generated configureAndrew Waterman2-0/+3478
2013-08-23Reflect changes to ISAAndrew Waterman47-2570/+487
Conflicts: isa/Makefile
2013-08-23Merge pull request #1 from smirolo/configureSebastien Mirolo6-14/+60
feature: add autoconf
2013-08-12Merge branch 'master' of git://github.com/ucb-bar/riscv-tests into configureSebastien Mirolo4-174/+2
2013-07-25Remove JALR static hintsAndrew Waterman4-174/+2
2013-07-24feature: add autoconfSebastien Mirolo6-14/+60
2013-06-14removed bad mt testHenry Cook1-1/+0
2013-06-13multithreading tests from 152 lab 5Henry Cook285-0/+60428
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