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2017-05-18Merge pull request #52 from riscv/vcs_sim_cmdMegan Wachs1-1/+1
2017-05-18debug: Correct the calling for a 32-bit simulation targetMegan Wachs1-1/+1
2017-05-17Manually assemble bad shift amount, since assembler rejectsAndrew Waterman1-1/+1
2017-05-17Shorten the debug testsPalmer Dabbelt1-4/+4
2017-05-17Merge pull request #49 from riscv/no_examine_targetPalmer Dabbelt1-1/+10
2017-05-17Show the debug logs to stdout, to avoid travis timeoutsPalmer Dabbelt1-1/+1
2017-05-16debug: remove unused auto_int functionMegan Wachs1-3/+0
2017-05-16debug: Allow skipping the ExamineTarget task.Megan Wachs1-4/+9
2017-05-16debug: Allow skipping the ExamineTarget step by specifying misaMegan Wachs1-1/+8
2017-05-16Merge pull request #47 from riscv/debug-0.13Palmer Dabbelt21-188/+291
2017-05-16Change Spike's RAM location to match the linker scriptPalmer Dabbelt1-2/+2
2017-05-16Link the infinate loop at 0x10000000Palmer Dabbelt3-1/+3
2017-05-16Link in encoding.h instead of providing a path to itPalmer Dabbelt5-4/+5
2017-05-16debug: Update OpenOCD configs.Megan Wachs2-5/+4
2017-05-15Copy debug/programs to the build dir, so debug-check runsPalmer Dabbelt1-1/+2
2017-05-15Merge pull request #48 from riscv/testsPalmer Dabbelt4-106/+117
2017-05-15Disable another PRIV mention, for nowPalmer Dabbelt1-1/+2
2017-05-15Disable the tests that touch PRIV, it's not implemented yetPalmer Dabbelt1-62/+63
2017-05-15Have the openocd invocation match the spike invocationPalmer Dabbelt1-1/+1
2017-05-15Disable some failing tests for nowPalmer Dabbelt1-37/+40
2017-05-15Don't rely on Spike's default ISAPalmer Dabbelt1-1/+3
2017-05-15Don't use the RTOS, and do "reset halt"Palmer Dabbelt1-3/+4
2017-05-15Let Spike have the default amount of RAMPalmer Dabbelt1-1/+0
2017-05-15Don't build openocd here, it's in riscv-tools nowPalmer Dabbelt1-1/+5
2017-05-15debug: fix the make target for debug-checkMegan Wachs1-19/+2
2017-05-15debug: Use consistent 'sim_cmd' argument.Megan Wachs2-2/+2
2017-05-14Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs3-5/+12
2017-05-05Check UXL in sstatusAndrew Waterman2-5/+10
2017-05-05Test that superpage PTEs trap when PPN LSBs are setAndrew Waterman1-0/+18
2017-05-05Regularize control flow in dirty-bit testAndrew Waterman1-8/+12
2017-05-01Set ELF entry point correctlyAndrew Waterman2-5/+6
2017-04-26Set FS before reading F registersPalmer Dabbelt1-0/+4
2017-04-26Add abort() for benefit of benchmark codeAndrew Waterman1-0/+6
2017-04-18bump OpenOCD versionMegan Wachs1-1/+1
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops (...Megan Wachs5-5/+20
2017-04-18debug: Use RTOS OpenOCD for Spike for now.Megan Wachs1-1/+1
2017-04-17debug: Checkpoint restoring Spike functionalityMegan Wachs5-29/+51
2017-04-17Merge remote-tracking branch 'origin/newprogram' into debug-0.13Megan Wachs9-18/+42
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs66-1063/+763
2017-04-14Fix illegal-instruction test when S-mode is not implementedAndrew Waterman1-10/+14
2017-04-14debug: checkpoint trying to get 64 bit programs to compile as well.Megan Wachs1-0/+3
2017-04-14debug: checkpoint of trying to get simulation tests workingMegan Wachs8-9/+29
2017-04-14debug: working with newprogram branchMegan Wachs4-10/+11
2017-04-10Improve fp ldst/move tests; remove redundant fsgnj testsAndrew Waterman9-122/+126
2017-04-07Retrofit rv64mi-p-illegal to test vectored interruptsAndrew Waterman1-7/+41
2017-04-07Remove defunct IPI testsAndrew Waterman4-62/+0
2017-04-05Make ma_addr test work for systems with misaligned ld/stAndrew Waterman1-34/+66
2017-03-30Expand dirty-bit test to test MPRV and SUMAndrew Waterman1-27/+30
2017-03-30New PMP encodingAndrew Waterman2-10/+13
2017-03-29Prohibit relaxing the initial gp generationPalmer Dabbelt2-0/+6
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