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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-17 15:26:27 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-17 15:26:27 -0700 |
| commit | 019192fead976af698d16b090d75be2dc7da053e (patch) | |
| tree | f3373eb819a80eba0dc1ab2a71a42cf69e736c60 | |
| parent | 2b0193de9f7cb43d3b3c519fe8eff497ea738598 (diff) | |
| download | riscv-tests-019192fead976af698d16b090d75be2dc7da053e.zip riscv-tests-019192fead976af698d16b090d75be2dc7da053e.tar.gz riscv-tests-019192fead976af698d16b090d75be2dc7da053e.tar.bz2 | |
Manually assemble bad shift amount, since assembler rejects
Resolves #51
| -rw-r--r-- | isa/rv32mi/shamt.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv32mi/shamt.S b/isa/rv32mi/shamt.S index 2c92412..aa136b5 100644 --- a/isa/rv32mi/shamt.S +++ b/isa/rv32mi/shamt.S @@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); # Make sure slli with shamt[5] set is not legal. - TEST_CASE( 3, x0, 1, slli a0, a0, 32); + TEST_CASE( 3, x0, 1, .word 0x02051513); # slli a0, a0, 32 TEST_PASSFAIL |