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2022-05-27Remove ineffective tests.trigger_priorityTim Newsome1-2/+0
2022-05-25Address trigger has higher priority than alignmentTim Newsome1-0/+46
Used this test to confirm that https://github.com/riscv-software-src/riscv-isa-sim/pull/1013 works right.
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
Adjust test to work with that.
2022-04-25Add EbreakTest. (#380)Tim Newsome2-0/+62
* Add EbreakTest. Confirm correct behavior when somebody bakes an ebreak instruction into their code. * Forgot to commit ebreak.c
2022-04-07Make download test data const. (#378)Tim Newsome1-2/+2
That way it can go into flash.
2022-03-08Add Zfh and Svnapot to Spike ISA stringAndrew Waterman1-2/+2
Otherwise, "make run" doesn't work.
2022-03-03With new OpenOCD, gdb prints thread info differently (#373)Tim Newsome1-1/+2
It includes the name in quotes: ```* 2 Thread 1 "Current Execution" (Name: Current Execution) 0x10000100 in main``` Just ignore that part.
2022-03-03Add assert to MemorySampleTest. (#370)Tim Newsome1-0/+1
Now it will give slightly more helpful output if it fails.
2022-02-09Debug test to check that stepping doesn't inappropriately switch to Thread 1 ↵Greg Savin1-0/+21
(#369)
2022-01-06Add gdb.interact() for debug tests. (#367)Tim Newsome1-0/+18
This feature lets you easily interact with the gdb after the test has run to a certain point.
2021-11-29Fix TranslateTests. (#365)Tim Newsome2-5/+7
They used to set U, A, D, in intermediate page table entries which is no longer allowed.
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
The tests don't confirm that the order actually changes, but at least the code that does the work now is executed during the tests.
2021-11-12Create DisconnectTest. (#364)Tim Newsome2-32/+53
Disconnects from gdb, and then reconnects, making sure that didn't change any of the registers. This test will start passing when https://github.com/riscv/riscv-openocd/pull/661 merges.
2021-11-12Add timing output to DebugTurboStep. (#362)Tim Newsome1-1/+5
Useful for estimating interactive performance.
2021-10-05Remove slen. (#360)Tim Newsome4-22/+16
It's not an argument to spike anymore. Also switch testing the vector unit from multi-gdb to `-rtos hwthread`. This exposes a bug in OpenOCD (which is already fixed).
2021-07-22Fix #352 (#353)Daniel Lustig1-2/+2
Thanks to @pdonahue-ventana for pointing this out
2021-07-21Move the Svnapot test to its own folder (#351)Daniel Lustig4-1/+10
...since not all implementations will support it
2021-07-19Bump envAndrew Waterman1-20/+0
Fixes #350
2021-07-19Add a test for Svnapot (#349)Daniel Lustig2-0/+173
2021-07-19Debug tests: catch write to nonexistent trigger registers in entry.S (#348)Luke Wren1-0/+7
2021-06-29Update README.md (#342)mymatin1-1/+1
2021-06-08Tweaks for multispike. (#339)Tim Newsome3-9/+19
1. Don't run all tests in multi-spike. Extra coverage is negligible, and it just takes too long. 2. Increase a few timeouts.
2021-06-01Enable access to cycle counter before trying to write itAndrew Waterman1-0/+13
There are two reasons that writing the cycle counter might trap: - Because it's a read-only CSR - Because mcounteren.CY=0 or scounteren.CY=0 We want to make sure we're testing the first property, so set up the other bits accordingly.
2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome6-63/+70
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: ↵SLAMET RIANTO2-0/+2
(#337) Added "#define stvec mtvec" under __MACHINE_MODE ifdef. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵SLAMET RIANTO3-0/+52
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome9-40/+303
* Test debugging multiple spikes in a daisy chain. * Hugely speed up rbb_daisychain. Now 2 dual-hart spikes are less than 4x slower than a single dual-hart spike. * WIP * Test daisy chained homogeneous spike instances. For OpenOCD, this means we're checking that we can talk to multiple TAPs. Next up is heterogeneous testing. * Enable Sv48Test. Didn't mean to disable it with this commit. * Test authentication again. Another change I hadn't meant to push...
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome9-15/+103
* Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`.
2021-02-11Add early_applicable() to a few tests. (#325)Tim Newsome1-7/+8
It's faster to figure out there that the test is going to N/A.
2021-02-01Align mtvec in rv32mi-p-shamt testAndrew Waterman1-0/+1
Resolves #323
2021-02-01Prevent GCC from pattern-matching the memset implementationAndrew Waterman1-1/+1
Otherwise, we get infinite recursion. Resolves #321 Resolves #322
2021-01-25Smoketest that vl and vtype can be modified. (#320)Tim Newsome2-29/+12
2021-01-08Don't rely on the implementation-specific WFI time limit (#318)Paul Donahue1-18/+0
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset * Remove testcase that relies on the implementation-specific WFI time limit being 0.
2021-01-08Disable V extension when compiler doesn't support it. (#317)Tim Newsome1-2/+24
This allows the vast majority of these tests to work with compilers that don't support the V extension yet, which is helpful for people who aren't using a vector branch of the compiler. Specifically, this will hopefully allow us to run regression tests against OpenOCD on every change, per https://github.com/riscv/riscv-openocd/pull/563.
2021-01-07Park other harts in TranslateTest. (#313)Tim Newsome1-0/+1
This fixes an intermitten failure when running these tests.
2021-01-07Stop testing `-rtos riscv`. (#314)Tim Newsome2-23/+3
As of tomorrow that feature is officially no longer supported in OpenOCD, so stop testing it.
2021-01-04Disable rv32ua/rv64ua LR/SC test case 4 (#316)Ben Marshall1-8/+14
- After discussion in riscv/riscv-tests#315, disable this test case, as it makes implementation assumptions which are not valid with respect to the specification. - Leave code present but commented out. On branch dev/benm-disable-lrsc-test-4 Changes to be committed: modified: isa/rv64ua/lrsc.S
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome7-1/+14
HiFiveUnleashed-flash fails som address translation tests. Possibly that would be fixed when https://github.com/riscv/riscv-tests/pull/313 merges.
2020-12-18Add test for new OpenOCD `riscv info` command. (#310)Tim Newsome1-0/+13
2020-12-18Revive and expand invalid read test. (#309)Tim Newsome1-12/+19
This test would have found https://github.com/riscv/riscv-openocd/issues/559.
2020-12-16Refactor rv64ud structural test to match format of other tests (#311)Kathlene Hurt1-11/+13
* Refactored rv64ud structural test to use pass/fail macros and test numbers * More clean up so test actually jumps to fail label
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome10-1/+104
2020-12-08Add rd=x0 test case to csr test (#308)Takahiro1-0/+1
2020-12-07Fix minor typo (#307)Takahiro1-1/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman19-38/+6
Resolves #303
2020-11-11add zfh (float16) test case and related macros (#301)Chih-Min Chao26-0/+769
* ext: add zfh extension test case and related macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * build: add zfh to target Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-10-19use registers present on rv32e (#299)Sandeep Rajendran1-4/+4
2020-10-15bump env (#298)Sandeep Rajendran1-14/+14
2020-10-08Expose registers on all harts in openocd cfgs (#297)Samuel Obuch2-4/+10
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