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2020-10-02Modify PMP benchmark to detect granularity (#295)Moritz Schneider1-10/+24
2020-08-31Add test for `riscv repeat_read`. (#293)Tim Newsome1-0/+34
2020-08-12Point people at a compiler that supports vectors. (#290)Tim Newsome1-1/+2
Addresses #289.
2020-08-06Add enable_rtos_riscv (#288)Tim Newsome1-0/+2
This is now required to use `-rtos riscv`. Addresses the aside mentioned in #287.
2020-07-14bump env to fix #286Andrew Waterman1-14/+14
2020-07-01Make pylint happy. (#285)Tim Newsome1-0/+1
2020-06-25Add manual hwbp test. (#283)Tim Newsome4-0/+98
Make sure OpenOCD cooperates when a user sets a trigger by writing tselect/tdata* directly.
2020-06-25Create a more sophisticated vector test (#284)Tim Newsome4-10/+248
* WIP * WIP * Vector test seems to work well with spike. * Check a0 in case the program didn't work right. * Return not applicable if compile doesn't support V
2020-05-26Test semihosting calls (#280)Tim Newsome9-5/+205
* Add a basic semihosting test. * Need to configure semihosting on each target. * WIP * Parse "cannot insert breakpoint" message. Also use sys.exit instead of exit, per new pylint's suggestion.
2020-05-18Parse "cannot insert breakpoint" message. (#279)Tim Newsome1-1/+8
Also use sys.exit instead of exit, per new pylint's suggestion.
2020-05-13Update env (#275)Paul Donahue1-5/+19
2020-04-17The HTIF device must live in its own page since it is (generally) a ↵Adrian Harris1-0/+1
bus/hardware device (#274)
2020-04-10Make TooManyHwbp more thorough. (#272)Tim Newsome1-1/+6
Test the behavior described in https://github.com/riscv/riscv-openocd/issues/76.
2020-04-10Change slen to a value that spike supports. (#271)Tim Newsome1-1/+3
2020-03-29Add debug-check-fast target forAndrew Waterman1-0/+4
This isn't appropriate for regression-testing the debug infrastructure, but is useful as a quick sanity check for unrelated CI runs, where we're just trying to make sure integration isn't totally borked.
2020-03-26Improve address translation tests (#261)Tim Newsome4-35/+59
* Improve address translation tests. Check that the mode we're testing is supported by hardware before running the test. Test with high address bits set, which catches a bug in OpenOCD. * Turn off PMP for address translation test. Otherwise it doesn't pass on HiFive Unleashed. * Run TranslateTest on random hart. Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work.
2020-03-26Write a NOP program in PrivRw test. (#260)Tim Newsome2-9/+8
Otherwise it only passes intermittently when I change _start, which is very confusing.
2020-03-21Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5Andrew Waterman1-7/+7
2020-03-21Move self-modifying 'fence.i' ops to .data memory section (#269)WRansohoff1-6/+14
Co-authored-by: WRR <-@->
2020-03-19Fix comments error in fmin.S (#267)Mohanson2-4/+4
2020-03-18Spike changed --varch syntax (#257)Tim Newsome1-2/+2
This was changed by https://github.com/riscv/riscv-isa-sim/pull/417
2020-03-18Specify misa for HiFive Unleashed. (#259)Tim Newsome1-0/+2
This saves a few seconds every time I run any test.
2020-03-18Have both rs=rd and rs!=rd cases in csr.S (#263)Takahiro1-12/+15
2020-03-18Fix shamt.S header (#264)Takahiro1-2/+2
2020-03-16Add a test case rs = rd to jalr.S (#258)Takahiro1-0/+16
2020-03-11Add comment explaining convoluted rv64mi-p-scall behaviorAndrew Waterman1-0/+6
2020-03-11Revert "scall: make the intention of the test in machine mode more clear (#246)"Andrew Waterman1-6/+1
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c. Resolves #256
2020-03-11Setup a multilevel page table to avoid misaligned superpages caused by ↵Cedric Orban1-0/+4
variable DRAM_BASE (#255) * setup a multilevel page table to avoid misaligned superpages * Revert "setup a multilevel page table to avoid misaligned superpages" This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5. * statically fail if DRAM_BASE is not superpage-aligned
2020-03-06Don't assume reset state of mscratch (#254)Paul Donahue2-13/+13
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset
2020-03-05bump env (#253)Han-Kuan Chen1-12/+12
2020-03-05Bump riscv-test-env (#252)Andrew Waterman1-5/+17
2020-03-05Clean up gdb parsing code. (#247)Tim Newsome1-42/+32
Also fix bug in parsing nan.
2020-03-05Add a simple mechanism to skip tests on targets. (#251)Tim Newsome2-1/+9
2020-03-02enable rv32e compatability by replacing reg x29 with reg x7 (#250)Cedric Orban1-12/+12
2020-02-27bump envAndrew Waterman1-10/+5
2020-02-21scall: make the intention of the test in machine mode more clear (#246)Nils Asmussen1-1/+6
2020-02-20Fix rv64mi-p-csr on systems with FPUsAndrew Waterman1-2/+3
3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because of the value of TESTNUM at the point an expected exception was taken. Fix by moving the new tests earlier in the program.
2020-02-14Add tests for vector register access (#244)Tim Newsome5-34/+137
* WIP * Add vector register smoketest. Also redo the gdb value parsing code to accommodate the more complicated way that vector registers look. * Test vector access a little more thoroughly. * Revert unnecessary changes.
2020-02-11Generate very different values on different harts. (#238)Tim Newsome2-4/+5
This way if you end up reading a value that you suspect might be coming from another hart/register, you can clearly see where it came from.
2020-02-11Run OpenOCD output through spike-dasm. (#239)Tim Newsome1-3/+9
If it's in the path, at least. This way you get human readable assembly in the log instead of hex values.
2020-02-11Look for \bmain\b instead of ' main '. (#237)Tim Newsome1-2/+2
2020-02-08Solves https://github.com/riscv/riscv-tests/issues/241 : Each mhartid has ↵Sho Nakatani1-2/+2
the same size of stack & TLS. (#242)
2020-01-31Added CSR test cases on whether writing 0 to CSR works, as that might get ↵Torbjørn Viem Ness1-0/+2
overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236)
2020-01-15Force DMI busy in all tests. (#235)Tim Newsome2-15/+44
This catches more corner cases where this may be a problem.
2020-01-09Smoke test virtual address translation support. (#233)Tim Newsome6-13/+231
* WIP * Smoke test virtual address support. Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as large as possible pages to 1:1 map the rest of RAM so those sizes do get minimal coverage as well.
2019-12-28benchmarks: Disassemble .text.init section (#230)Albert Ou1-1/+1
2019-12-24submodule: bump env version (#229)Chih-Min Chao1-5/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome9-7/+27
`make` now takes 31s, `make all` takes 1m53s. The new CheckMisa test ensures that the misa value specified in the configuration is correct.
2019-12-18Tell people where to get software. (#226)Tim Newsome1-3/+9
2019-12-10benchmarks: Simplify TLS initialisation (#224)James Clarke3-19/+5
The symbols used to query the size of .tdata and .tbss need not be thread-local themselves; instead, make them linker script-provided non-thread-local symbols.
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