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2025-12-02[debug] check triggers exist in icount/itrigger/etrigger test (#617)HEADmasterZane2-1/+22
2025-11-24[debug] Misc debug fixes (#632)hirooih4-18/+19
2025-11-24debug: test implements_page_virtual_memory before executing sfence.vma instru...hirooih1-7/+8
2025-11-18[debug] Add support_abstractauto option to Spike target (#635)Nadime Barhoumi1-2/+5
2025-11-16Clear mcountinhibit.ir in minstret test to ensure minstret increments. (#634)Luke Wren1-0/+9
2025-11-06[debug] Support mcontrol6 in TriggerDmode test (#620)Zane3-4/+29
2025-10-30Improve Ziccid test to handle in-order fetch ruleAndrew Waterman1-5/+61
2025-10-24Fix duplicate mulh test case in rv32m tests (#630)404allen4041-1/+1
2025-10-14Merge pull request #629 from aman4150/masterAman2-0/+4
2025-06-13Merge pull request #624 from riscv-software-src/ziccidAndrew Waterman3-2/+61
2025-06-13Add Ziccid testAndrew Waterman3-2/+61
2025-06-12Replace floating magic constant by macro (#623)Andrew Waterman17-43/+61
2025-06-10apply nInffChih-Min Chao4-4/+4
2025-06-10apply InffChih-Min Chao5-5/+5
2025-06-10apply nInfdChih-Min Chao3-3/+3
2025-06-10apply InfdChih-Min Chao4-4/+4
2025-06-10apply nInfhChih-Min Chao1-1/+1
2025-06-10apply InfhChih-Min Chao2-2/+2
2025-06-10apply sNaNhChih-Min Chao2-2/+2
2025-06-10apply qNaNfChih-Min Chao4-9/+9
2025-06-10apply qNaNdChih-Min Chao4-5/+5
2025-06-10apply sNaNdChih-Min Chao3-5/+5
2025-06-10apply sNaNfChih-Min Chao3-5/+5
2025-06-10macro: define [sq]NaN[dfh] and [n]Inf[dfh]Chih-Min Chao1-0/+18
2025-04-28CI: Bump GitHub actions to latest versions (#619)Andrew Waterman2-11/+11
2025-04-18Fix rv32ud-p-fcvt_w and -recoding being redundant with rv32ufAndrew Waterman3-3/+7
2025-04-18configure: do autoupdateAriel Xiong1-4/+4
2025-04-15Remove use of qNaN/sNaN in a different way to fix LLVM build (#613)Andrew Waterman9-69/+87
2025-04-15Fix rv64ua-amomaxu_w and rv64ua-amominu_w testcases for rv32 (#611)etterli2-0/+8
2025-04-14Remove use of qNaN/sNaN to fix LLVM build (#612)Andrew Waterman9-22/+35
2025-04-10Add test for pmpaddr[G-1] edge cases (#609)Tim Hutt4-0/+164
2025-04-07Add instret_overflow testAndrew Waterman4-0/+52
2025-04-07Moving env forward (#607)Ariel Xiong1-0/+0
2025-04-03Removed irrelevant test (#605)Kathlene Magnus2-71/+0
2025-02-28Merge pull request #603 from riscv-software-src/bmark_compileJerry Zhao1-4/+11
2025-02-24Compile non-vec benchmarks for rv64gcJerry Zhao1-4/+11
2025-02-07Added instructions to handle Rs1 and Rd dependency in load-store bypass seque...splinedrive1-0/+14
2025-01-29Add Load-Store and Store-Load Bypass Tests for Forwarding in Pipelined CPU (#...splinedrive7-5/+301
2024-11-18Suppress implicit-int and implicit-function-declaration warnings in Dhrystone...Tommy Murphy1-1/+1
2024-11-16Fix the typo in the Makefrag for the reference to 2-stage-translation.S (#596)Kun Lu1-1/+1
2024-11-11Add hypervisor 2-stage translation test (#558)heiyuen19993-1/+147
2024-11-11[debug] Add sfence.vma in the disable_pmp (#537)lzbro2-0/+7
2024-11-11Merge pull request #535 from lz-bro/set_pmp_denyAnatoly Parshintsev3-0/+33
2024-11-09[debug] Set PMP to create bad addressliangzhen3-0/+33
2024-11-08[debug] Clear interrupt enable and pending in disable_timer (#538)lzbro2-1/+4
2024-10-31[debug] Support more SREC type in MemTestBlock (#589)lzbro1-3/+17
2024-10-31suppress new lint checks in old code (#590)Andrew Waterman1-0/+4
2024-09-06Merge pull request #581 from en-sc/en-sc/reserve-trigger-fix-propperEvgeniy Naydanov1-21/+59
2024-09-06[debug] Reserve triggers propperly in HwbpManualEvgeniy Naydanov1-21/+59
2024-09-05Merge pull request #580 from en-sc/en-sc/reserve-trigger-fixEvgeniy Naydanov1-1/+1
generated by cgit v1.1 at 2025-12-27 21:25:43 +0000