diff options
Diffstat (limited to 'isa')
| -rw-r--r-- | isa/rv64si/ma_fetch.S | 40 |
1 files changed, 31 insertions, 9 deletions
diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S index 7d2adec..22eadc9 100644 --- a/isa/rv64si/ma_fetch.S +++ b/isa/rv64si/ma_fetch.S @@ -107,13 +107,41 @@ RVTEST_CODE_BEGIN 2: #ifdef __MACHINE_MODE - # RVC cannot be disabled if doing so would cause a misaligned instruction + # Skip if C cannot be enabled + csrsi misa, 1 << ('c' - 'a') + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + beqz t2, pass + + # Skip if C cannot be disabled + csrci misa, 1 << ('c' - 'a') + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + bnez t2, pass + + # Skip if clearing misa.C does not set IALIGN=32 + csrr t0, mepc + la t1, 1f + addi t1, t1, 2 + csrw mepc, t1 + j 1f + + .option rvc + c.nop +1: + j pass + .option norvc +2: + csrw mepc, t0 + csrsi misa, 1 << ('c' - 'a') + + # IALIGN=32 cannot be set if doing so would cause a misaligned instruction # exception on the next instruction fetch. (This test assumes no other # extensions that support misalignment are present.) li TESTNUM, 8 csrr t2, misa andi t2, t2, 1 << ('c' - 'a') - beqz t2, 2f + beqz t2, pass .option rvc c.nop @@ -126,18 +154,13 @@ RVTEST_CODE_BEGIN andi t2, t2, 1 << ('c' - 'a') beqz t2, fail - # When RVC is disabled, mret to a misaligned mepc should succeed, + # IALIGN=32, mret to a misaligned mepc should succeed, # masking off mepc[1]. la t0, 1f addi t0, t0, -2 csrw mepc, t0 - # Try to disable RVC; if it can't be disabled, skip the test. csrci misa, 1 << ('c' - 'a') - csrr t2, misa - andi t2, t2, 1 << ('c' - 'a') - bnez t2, 2f - li t2, MSTATUS_MPP csrs mstatus, t2 mret @@ -148,7 +171,6 @@ RVTEST_CODE_BEGIN beqz x0, 1f 1: csrsi misa, 1 << ('c' - 'a') -2: #endif j pass |