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-rw-r--r--isa/rv32ui/srli.S66
1 files changed, 66 insertions, 0 deletions
diff --git a/isa/rv32ui/srli.S b/isa/rv32ui/srli.S
new file mode 100644
index 0000000..bcda999
--- /dev/null
+++ b/isa/rv32ui/srli.S
@@ -0,0 +1,66 @@
+#*****************************************************************************
+# srli.S
+#-----------------------------------------------------------------------------
+#
+# Test srli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_OP( 2, srli, 0x80000000, 0x80000000, 0 );
+ TEST_IMM_OP( 3, srli, 0xc0000000, 0x80000000, 1 );
+ TEST_IMM_OP( 4, srli, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_OP( 5, srli, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_OP( 6, srli, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_OP( 7, srli, 0xffffffff, 0xffffffff, 0 );
+ TEST_IMM_OP( 8, srli, 0xffffffff, 0xffffffff, 1 );
+ TEST_IMM_OP( 9, srli, 0xffffffff, 0xffffffff, 7 );
+ TEST_IMM_OP( 10, srli, 0xffffffff, 0xffffffff, 14 );
+ TEST_IMM_OP( 11, srli, 0xffffffff, 0xffffffff, 31 );
+
+ TEST_IMM_OP( 12, srli, 0x21212121, 0x21212121, 0 );
+ TEST_IMM_OP( 13, srli, 0x10909090, 0x21212121, 1 );
+ TEST_IMM_OP( 14, srli, 0x00424242, 0x21212121, 7 );
+ TEST_IMM_OP( 15, srli, 0x00008484, 0x21212121, 14 );
+ TEST_IMM_OP( 16, srli, 0x00000000, 0x21212121, 31 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_SRC1_EQ_DEST( 17, srli, 0xff000000, 0x80000000, 7 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_IMM_DEST_BYPASS( 18, 0, srli, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_DEST_BYPASS( 19, 1, srli, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_DEST_BYPASS( 20, 2, srli, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0xff000000, 0x80000000, 7 );
+ TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0xfffe0000, 0x80000000, 14 );
+ TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0xffffffff, 0x80000001, 31 );
+
+ TEST_IMM_ZEROSRC1( 24, srli, 0, 32 );
+ TEST_IMM_ZERODEST( 25, srli, 33, 50 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END