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-rw-r--r--debug/testlib.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/debug/testlib.py b/debug/testlib.py
index 3aaa542..735dcba 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -117,6 +117,7 @@ class Spike(object):
isa = "RV%dG" % harts[0].xlen
cmd += ["--isa", isa]
+ cmd += ["--debug-auth"]
assert len(set(t.ram for t in harts)) == 1, \
"All spike harts must have the same RAM layout"