diff options
| -rw-r--r-- | debug/targets/RISC-V/spike-2-hwthread.cfg | 7 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike-2.cfg | 7 |
2 files changed, 10 insertions, 4 deletions
diff --git a/debug/targets/RISC-V/spike-2-hwthread.cfg b/debug/targets/RISC-V/spike-2-hwthread.cfg index 94bac00..c378a45 100644 --- a/debug/targets/RISC-V/spike-2-hwthread.cfg +++ b/debug/targets/RISC-V/spike-2-hwthread.cfg @@ -19,8 +19,11 @@ gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. -riscv expose_csrs 2288 -riscv expose_custom 1,12345-12348 +foreach t [target names] { + targets $t + riscv expose_csrs 2288 + riscv expose_custom 1,12345-12348 +} init diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg index 0eadb89..640fba9 100644 --- a/debug/targets/RISC-V/spike-2.cfg +++ b/debug/targets/RISC-V/spike-2.cfg @@ -18,8 +18,11 @@ gdb_report_register_access_error enable # Expose an unimplemented CSR so we can test non-existent register access # behavior. -riscv expose_csrs 2288 -riscv expose_custom 1,12345-12348 +foreach t [target names] { + targets $t + riscv expose_csrs 2288 + riscv expose_custom 1,12345-12348 +} init |