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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-04-22 14:56:59 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-04-22 14:56:59 -0700 |
commit | 81ad66f25ce4c15180e558696961bd8eaf967fea (patch) | |
tree | d70676fb1d11a4a66a268f7860d3ef7d469987fe /isa/rv64uv/vmsv.S | |
download | riscv-tests-81ad66f25ce4c15180e558696961bd8eaf967fea.zip riscv-tests-81ad66f25ce4c15180e558696961bd8eaf967fea.tar.gz riscv-tests-81ad66f25ce4c15180e558696961bd8eaf967fea.tar.bz2 |
initial commit
Diffstat (limited to 'isa/rv64uv/vmsv.S')
-rw-r--r-- | isa/rv64uv/vmsv.S | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/isa/rv64uv/vmsv.S b/isa/rv64uv/vmsv.S new file mode 100644 index 0000000..732f660 --- /dev/null +++ b/isa/rv64uv/vmsv.S @@ -0,0 +1,53 @@ +#***************************************************************************** +# vmsv.S +#----------------------------------------------------------------------------- +# +# Test vmsv instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + li a2,2048 + vvcfgivl a2,a2,3,0 + + li a3,-1 + vmsv vx2,a3 + lui a0,%hi(vtcode) + vf %lo(vtcode)(a0) + la a4,dest + vsd vx2,a4 + fence.v.l + + li a1,0 +loop: + ld a0,0(a4) + addi x28,a1,2 + bne a0,a1,fail + addi a4,a4,8 + addi a1,a1,1 + bne a1,a2,loop + j pass + +vtcode: + utidx x1 + addi x1,x1,1 + add x2,x1,x2 + stop + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +dest: + .skip 16384 + +RVTEST_DATA_END |