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authorAndrew Waterman <andrew@sifive.com>2017-03-21 16:46:43 -0700
committerAndrew Waterman <andrew@sifive.com>2017-03-21 16:46:43 -0700
commit96ef658f1fce0f1b4cce468ad7fa3ff453b9ebac (patch)
treeef6d18dbf4119755c469ed90948839ac6af28bbf /isa/rv64ui
parent33a1beb24e65c32aa8e2f2547da27eb3e24c4cc9 (diff)
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Avoid x3 (gp), which is now TESTNUM
Diffstat (limited to 'isa/rv64ui')
-rw-r--r--isa/rv64ui/jal.S4
-rw-r--r--isa/rv64ui/lb.S16
-rw-r--r--isa/rv64ui/lbu.S16
-rw-r--r--isa/rv64ui/ld.S16
-rw-r--r--isa/rv64ui/lh.S16
-rw-r--r--isa/rv64ui/lhu.S16
-rw-r--r--isa/rv64ui/lw.S16
-rw-r--r--isa/rv64ui/lwu.S16
-rw-r--r--isa/rv64ui/sb.S8
-rw-r--r--isa/rv64ui/sd.S8
-rw-r--r--isa/rv64ui/sh.S8
-rw-r--r--isa/rv64ui/sw.S8
12 files changed, 74 insertions, 74 deletions
diff --git a/isa/rv64ui/jal.S b/isa/rv64ui/jal.S
index f7f299d..00c65d8 100644
--- a/isa/rv64ui/jal.S
+++ b/isa/rv64ui/jal.S
@@ -21,7 +21,7 @@ test_2:
li TESTNUM, 2
li ra, 0
- jal x3, target_2
+ jal x4, target_2
linkaddr_2:
nop
nop
@@ -30,7 +30,7 @@ linkaddr_2:
target_2:
la x2, linkaddr_2
- bne x2, x3, fail
+ bne x2, x4, fail
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
diff --git a/isa/rv64ui/lb.S b/isa/rv64ui/lb.S
index 277b03e..856dfe9 100644
--- a/isa/rv64ui/lb.S
+++ b/isa/rv64ui/lb.S
@@ -31,18 +31,18 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0xffffffffffffffff, \
+ TEST_CASE( 10, x5, 0xffffffffffffffff, \
la x1, tdat; \
addi x1, x1, -32; \
- lb x3, 32(x1); \
+ lb x5, 32(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0x0000000000000000, \
+ TEST_CASE( 11, x5, 0x0000000000000000, \
la x1, tdat; \
addi x1, x1, -6; \
- lb x3, 7(x1); \
+ lb x5, 7(x1); \
)
#-------------------------------------------------------------
@@ -62,14 +62,14 @@ RVTEST_CODE_BEGIN
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
- la x3, tdat; \
- lb x2, 0(x3); \
+ la x5, tdat; \
+ lb x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
- la x3, tdat; \
- lb x2, 0(x3); \
+ la x5, tdat; \
+ lb x2, 0(x5); \
nop; \
li x2, 2; \
)
diff --git a/isa/rv64ui/lbu.S b/isa/rv64ui/lbu.S
index 5f4c2fe..adc3a05 100644
--- a/isa/rv64ui/lbu.S
+++ b/isa/rv64ui/lbu.S
@@ -31,18 +31,18 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x00000000000000ff, \
+ TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
- lbu x3, 32(x1); \
+ lbu x5, 32(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0x0000000000000000, \
+ TEST_CASE( 11, x5, 0x0000000000000000, \
la x1, tdat; \
addi x1, x1, -6; \
- lbu x3, 7(x1); \
+ lbu x5, 7(x1); \
)
#-------------------------------------------------------------
@@ -62,14 +62,14 @@ RVTEST_CODE_BEGIN
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
- la x3, tdat; \
- lbu x2, 0(x3); \
+ la x5, tdat; \
+ lbu x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
- la x3, tdat; \
- lbu x2, 0(x3); \
+ la x5, tdat; \
+ lbu x2, 0(x5); \
nop; \
li x2, 2; \
)
diff --git a/isa/rv64ui/ld.S b/isa/rv64ui/ld.S
index 62fe4e5..948c34b 100644
--- a/isa/rv64ui/ld.S
+++ b/isa/rv64ui/ld.S
@@ -31,18 +31,18 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x00ff00ff00ff00ff, \
+ TEST_CASE( 10, x5, 0x00ff00ff00ff00ff, \
la x1, tdat; \
addi x1, x1, -32; \
- ld x3, 32(x1); \
+ ld x5, 32(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0xff00ff00ff00ff00, \
+ TEST_CASE( 11, x5, 0xff00ff00ff00ff00, \
la x1, tdat; \
addi x1, x1, -3; \
- ld x3, 11(x1); \
+ ld x5, 11(x1); \
)
#-------------------------------------------------------------
@@ -62,14 +62,14 @@ RVTEST_CODE_BEGIN
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
- la x3, tdat; \
- ld x2, 0(x3); \
+ la x5, tdat; \
+ ld x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
- la x3, tdat; \
- ld x2, 0(x3); \
+ la x5, tdat; \
+ ld x2, 0(x5); \
nop; \
li x2, 2; \
)
diff --git a/isa/rv64ui/lh.S b/isa/rv64ui/lh.S
index decacda..338ed69 100644
--- a/isa/rv64ui/lh.S
+++ b/isa/rv64ui/lh.S
@@ -31,18 +31,18 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x00000000000000ff, \
+ TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
- lh x3, 32(x1); \
+ lh x5, 32(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0xffffffffffffff00, \
+ TEST_CASE( 11, x5, 0xffffffffffffff00, \
la x1, tdat; \
addi x1, x1, -5; \
- lh x3, 7(x1); \
+ lh x5, 7(x1); \
)
#-------------------------------------------------------------
@@ -62,14 +62,14 @@ RVTEST_CODE_BEGIN
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
- la x3, tdat; \
- lh x2, 0(x3); \
+ la x5, tdat; \
+ lh x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
- la x3, tdat; \
- lh x2, 0(x3); \
+ la x5, tdat; \
+ lh x2, 0(x5); \
nop; \
li x2, 2; \
)
diff --git a/isa/rv64ui/lhu.S b/isa/rv64ui/lhu.S
index 5a55724..a4cc49b 100644
--- a/isa/rv64ui/lhu.S
+++ b/isa/rv64ui/lhu.S
@@ -31,18 +31,18 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x00000000000000ff, \
+ TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
- lhu x3, 32(x1); \
+ lhu x5, 32(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0x000000000000ff00, \
+ TEST_CASE( 11, x5, 0x000000000000ff00, \
la x1, tdat; \
addi x1, x1, -5; \
- lhu x3, 7(x1); \
+ lhu x5, 7(x1); \
)
#-------------------------------------------------------------
@@ -62,14 +62,14 @@ RVTEST_CODE_BEGIN
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
- la x3, tdat; \
- lhu x2, 0(x3); \
+ la x5, tdat; \
+ lhu x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
- la x3, tdat; \
- lhu x2, 0(x3); \
+ la x5, tdat; \
+ lhu x2, 0(x5); \
nop; \
li x2, 2; \
)
diff --git a/isa/rv64ui/lw.S b/isa/rv64ui/lw.S
index 02a12c0..40a73f1 100644
--- a/isa/rv64ui/lw.S
+++ b/isa/rv64ui/lw.S
@@ -31,18 +31,18 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x0000000000ff00ff, \
+ TEST_CASE( 10, x5, 0x0000000000ff00ff, \
la x1, tdat; \
addi x1, x1, -32; \
- lw x3, 32(x1); \
+ lw x5, 32(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0xffffffffff00ff00, \
+ TEST_CASE( 11, x5, 0xffffffffff00ff00, \
la x1, tdat; \
addi x1, x1, -3; \
- lw x3, 7(x1); \
+ lw x5, 7(x1); \
)
#-------------------------------------------------------------
@@ -62,14 +62,14 @@ RVTEST_CODE_BEGIN
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
- la x3, tdat; \
- lw x2, 0(x3); \
+ la x5, tdat; \
+ lw x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
- la x3, tdat; \
- lw x2, 0(x3); \
+ la x5, tdat; \
+ lw x2, 0(x5); \
nop; \
li x2, 2; \
)
diff --git a/isa/rv64ui/lwu.S b/isa/rv64ui/lwu.S
index 1ca17b1..9f7cf67 100644
--- a/isa/rv64ui/lwu.S
+++ b/isa/rv64ui/lwu.S
@@ -31,18 +31,18 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x0000000000ff00ff, \
+ TEST_CASE( 10, x5, 0x0000000000ff00ff, \
la x1, tdat; \
addi x1, x1, -32; \
- lwu x3, 32(x1); \
+ lwu x5, 32(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0x00000000ff00ff00, \
+ TEST_CASE( 11, x5, 0x00000000ff00ff00, \
la x1, tdat; \
addi x1, x1, -3; \
- lwu x3, 7(x1); \
+ lwu x5, 7(x1); \
)
#-------------------------------------------------------------
@@ -62,14 +62,14 @@ RVTEST_CODE_BEGIN
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
- la x3, tdat; \
- lwu x2, 0(x3); \
+ la x5, tdat; \
+ lwu x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
- la x3, tdat; \
- lwu x2, 0(x3); \
+ la x5, tdat; \
+ lwu x2, 0(x5); \
nop; \
li x2, 2; \
)
diff --git a/isa/rv64ui/sb.S b/isa/rv64ui/sb.S
index 17ab2e2..19e32d6 100644
--- a/isa/rv64ui/sb.S
+++ b/isa/rv64ui/sb.S
@@ -31,23 +31,23 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x78, \
+ TEST_CASE( 10, x5, 0x78, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sb x2, 32(x4); \
- lb x3, 0(x1); \
+ lb x5, 0(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0xffffffffffffff98, \
+ TEST_CASE( 11, x5, 0xffffffffffffff98, \
la x1, tdat9; \
li x2, 0x00003098; \
addi x1, x1, -6; \
sb x2, 7(x1); \
la x4, tdat10; \
- lb x3, 0(x4); \
+ lb x5, 0(x4); \
)
#-------------------------------------------------------------
diff --git a/isa/rv64ui/sd.S b/isa/rv64ui/sd.S
index f9d83b7..b6fd66d 100644
--- a/isa/rv64ui/sd.S
+++ b/isa/rv64ui/sd.S
@@ -31,23 +31,23 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x1234567812345678, \
+ TEST_CASE( 10, x5, 0x1234567812345678, \
la x1, tdat9; \
li x2, 0x1234567812345678; \
addi x4, x1, -32; \
sd x2, 32(x4); \
- ld x3, 0(x1); \
+ ld x5, 0(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0x5821309858213098, \
+ TEST_CASE( 11, x5, 0x5821309858213098, \
la x1, tdat9; \
li x2, 0x5821309858213098; \
addi x1, x1, -3; \
sd x2, 11(x1); \
la x4, tdat10; \
- ld x3, 0(x4); \
+ ld x5, 0(x4); \
)
#-------------------------------------------------------------
diff --git a/isa/rv64ui/sh.S b/isa/rv64ui/sh.S
index 10897d4..ea9eb23 100644
--- a/isa/rv64ui/sh.S
+++ b/isa/rv64ui/sh.S
@@ -31,23 +31,23 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x5678, \
+ TEST_CASE( 10, x5, 0x5678, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sh x2, 32(x4); \
- lh x3, 0(x1); \
+ lh x5, 0(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0x3098, \
+ TEST_CASE( 11, x5, 0x3098, \
la x1, tdat9; \
li x2, 0x00003098; \
addi x1, x1, -5; \
sh x2, 7(x1); \
la x4, tdat10; \
- lh x3, 0(x4); \
+ lh x5, 0(x4); \
)
#-------------------------------------------------------------
diff --git a/isa/rv64ui/sw.S b/isa/rv64ui/sw.S
index 86b62fc..ab094b3 100644
--- a/isa/rv64ui/sw.S
+++ b/isa/rv64ui/sw.S
@@ -31,23 +31,23 @@ RVTEST_CODE_BEGIN
# Test with a negative base
- TEST_CASE( 10, x3, 0x12345678, \
+ TEST_CASE( 10, x5, 0x12345678, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sw x2, 32(x4); \
- lw x3, 0(x1); \
+ lw x5, 0(x1); \
)
# Test with unaligned base
- TEST_CASE( 11, x3, 0x58213098, \
+ TEST_CASE( 11, x5, 0x58213098, \
la x1, tdat9; \
li x2, 0x58213098; \
addi x1, x1, -3; \
sw x2, 7(x1); \
la x4, tdat10; \
- lw x3, 0(x4); \
+ lw x5, 0(x4); \
)
#-------------------------------------------------------------
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