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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-01 23:17:17 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-01 23:17:17 -0800 |
| commit | 367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c (patch) | |
| tree | 08f0c0c16a63ebe581681ca5abe9ea93d8a88915 /isa/rv64uf | |
| parent | b4e820b5a0007d5ca8ab1a5de2327d247a81a9aa (diff) | |
| download | riscv-tests-367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c.zip riscv-tests-367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c.tar.gz riscv-tests-367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c.tar.bz2 | |
Test FMIN/FMAX NaN behavior
See https://github.com/riscv/riscv-isa-sim/issues/76
Diffstat (limited to 'isa/rv64uf')
| -rw-r--r-- | isa/rv64uf/fmin.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/isa/rv64uf/fmin.S b/isa/rv64uf/fmin.S index a2650e5..5bbbf3f 100644 --- a/isa/rv64uf/fmin.S +++ b/isa/rv64uf/fmin.S @@ -31,6 +31,11 @@ RVTEST_CODE_BEGIN TEST_FP_OP2_S(16, fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 ); TEST_FP_OP2_S(17, fmax.s, 0, -1.0, -1.0, -2.0 ); + # FMIN(sNaN, x) = canonical NaN + TEST_FP_OP2_S(20, fmax.s, 0x10, qNaNf, sNaNf, 0); + # FMIN(qNaN, qNaN) = canonical NaN + TEST_FP_OP2_S(21, fmax.s, 0x00, qNaNf, NaN, NaN); + TEST_PASSFAIL RVTEST_CODE_END |