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| author | Torbjørn <tovine@users.noreply.github.com> | 2017-11-27 06:56:53 +0100 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2017-11-26 21:56:53 -0800 |
| commit | 49f478416cec9f73801fdc5dedf9955494be8c66 (patch) | |
| tree | ee07276de133354d01ba5efbf02514e2e841b25f /isa/rv64ud/fcvt.S | |
| parent | 018aea17aca9abb6221e1a59d943ecdd386cc8ec (diff) | |
| download | riscv-tests-49f478416cec9f73801fdc5dedf9955494be8c66.zip riscv-tests-49f478416cec9f73801fdc5dedf9955494be8c66.tar.gz riscv-tests-49f478416cec9f73801fdc5dedf9955494be8c66.tar.bz2 | |
Rv32ud tests (#108)
* Probably implemented the changes required to support fadd test for rv32ud
* Created test files in rv32ud, implemented working(?) test for ldst
* fclass, fcvt_w, fmin and recoding seem to be working now
* Got fdiv (and sqrt) tests working
* fmadd tests seem to work
* fcmp works
* [WIP] fcvt working, but lacks a 32-bit implementation of the final test
* Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST
* Added Makefrag for rv32ud tests and included in main isa Makefile
* Don't run 64-bit tests if the defined XLEN is 32
Diffstat (limited to 'isa/rv64ud/fcvt.S')
| -rw-r--r-- | isa/rv64ud/fcvt.S | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/isa/rv64ud/fcvt.S b/isa/rv64ud/fcvt.S index 4f25d07..98916b1 100644 --- a/isa/rv64ud/fcvt.S +++ b/isa/rv64ud/fcvt.S @@ -13,6 +13,15 @@ RVTEST_RV64UF RVTEST_CODE_BEGIN +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_INT_FP_OP_D + #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32 + + #undef TEST_FCVT_S_D + #define TEST_FCVT_S_D TEST_FCVT_S_D32 +#endif + #------------------------------------------------------------- # Arithmetic tests #------------------------------------------------------------- @@ -23,15 +32,18 @@ RVTEST_CODE_BEGIN TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2); TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2); +#if __riscv_xlen >= 64 TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2); TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2); TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2); TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2); +#endif TEST_FCVT_S_D(10, -1.5, -1.5) TEST_FCVT_D_S(11, -1.5, -1.5) +#if __riscv_xlen >= 64 TEST_CASE(12, a0, 0x7ff8000000000000, la a1, test_data_22; ld a2, 0(a1); @@ -40,6 +52,17 @@ RVTEST_CODE_BEGIN fcvt.d.s f2, f2; fmv.x.d a0, f2; ) +#else + TEST_CASE_D32(12, a0, a1, 0x7ff8000000000000, + la a1, test_data_22; + fld f2, 0(a1); + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fsd f2, 0(a1); + lw a0, 0(a1); + lw a1, 4(a1) + ) +#endif TEST_PASSFAIL |