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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:35:34 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:35:34 -0700 |
| commit | 2f00c0c1f26a10f93f4a133bec69f4d0b95df685 (patch) | |
| tree | 699ebd180e0de1076a2a511e5a2f133035dc8ca8 /isa/rv64sv/ma_utsd.S | |
| parent | ddf8212714fcb6dc240a71bd1e1f52e02fc208b0 (diff) | |
| download | riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.zip riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.tar.gz riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.tar.bz2 | |
add hwacha exception support
Diffstat (limited to 'isa/rv64sv/ma_utsd.S')
| -rw-r--r-- | isa/rv64sv/ma_utsd.S | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S index 3b9e094..ead6c2c 100644 --- a/isa/rv64sv/ma_utsd.S +++ b/isa/rv64sv/ma_utsd.S @@ -11,14 +11,16 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - mfpcr a3,cr0 - li a4,1 - slli a5,a4,8 - or a3,a3,a4 # enable traps - mtpcr a3,cr0 + setpcr status, SR_EI # enable interrupt la a3,handler - mtpcr a3,cr3 # set exception handler + mtpcr a3,evec # set exception handler + + mfpcr a3,status + li a4,(1 << IRQ_COP) + slli a4,a4,SR_IM_SHIFT + or a3,a3,a4 # enable IM[COP] + mtpcr a3,status vsetcfg 32,0 li a3,4 @@ -46,12 +48,12 @@ handler: li x28,2 # check cause - mfpcr a3,cr6 - li a4,29 + vxcptcause a3 + li a4,HWACHA_CAUSE_MISALIGNED_STORE bne a3,a4,fail # check vec irq aux - mfpcr a3,cr2 + vxcptaux a3 la a4, dest+1 bne a3,a4,fail |