initial commit

3 files changed, 189 insertions, 0 deletions

diff --git a/isa/rv64si/Makefile b/isa/rv64si/Makefile
new file mode 100644
index 0000000..c6db077
--- /dev/null
+++ b/isa/rv64si/Makefile
@@ -0,0 +1,99 @@
+#=======================================================================
+# Makefile for riscv-tests
+#-----------------------------------------------------------------------
+
+default: all
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+rv64si_sc_tests = \
+	coreid \
+
+rv64si_mc_tests = \
+	ipi \
+
+rv64si_sc_vec_tests = \
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_GCC = riscv-gcc
+RISCV_GCC_OPTS = -nostdlib -nostartfiles
+RISCV_OBJDUMP = riscv-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.data --section=.bss
+RISCV_SIM = riscv-isa-run
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.hex: %
+	elf2hex 16 16384 $< > $@
+
+%.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+%.out: %
+	$(RISCV_SIM) $< 2> $@
+
+rv64si_p_tests_bin = $(addprefix rv64si-p-, $(rv64si_sc_tests))
+rv64si_p_tests_dump = $(addsuffix .dump, $(rv64si_p_tests_bin))
+rv64si_p_tests_hex = $(addsuffix .hex, $(rv64si_p_tests_bin))
+rv64si_p_tests_out  = $(addsuffix .out,  $(rv64si_p_tests_bin))
+
+$(rv64si_p_tests_bin): rv64si-p-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/scalar -T../../env/p/link.ld $< -o $@
+
+rv64si_pm_tests_bin = $(addprefix rv64si-pm-, $(rv64si_mc_tests))
+rv64si_pm_tests_dump = $(addsuffix .dump, $(rv64si_pm_tests_bin))
+rv64si_pm_tests_hex = $(addsuffix .hex, $(rv64si_pm_tests_bin))
+rv64si_pm_tests_out  = $(addsuffix .out,  $(rv64si_pm_tests_bin))
+
+$(rv64si_pm_tests_bin): rv64si-pm-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pm -I../macros/scalar -T../../env/pm/link.ld $< -o $@
+
+rv64si_p_vec_tests_bin = $(addprefix rv64si-p-vec-, $(rv64si_sc_vec_tests))
+rv64si_p_vec_tests_dump = $(addsuffix .dump, $(rv64si_p_vec_tests_bin))
+rv64si_p_vec_tests_hex = $(addsuffix .hex, $(rv64si_p_vec_tests_bin))
+rv64si_p_vec_tests_out  = $(addsuffix .out,  $(rv64si_p_vec_tests_bin))
+
+$(rv64si_p_vec_tests_bin): rv64si-p-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/p -I../macros/vector -T../../env/p/link.ld $< -o $@
+
+rv64si_pt_vec_tests_bin = $(addprefix rv64si-pt-vec-, $(rv64si_sc_vec_tests))
+rv64si_pt_vec_tests_dump = $(addsuffix .dump, $(rv64si_pt_vec_tests_bin))
+rv64si_pt_vec_tests_hex = $(addsuffix .hex, $(rv64si_pt_vec_tests_bin))
+rv64si_pt_vec_tests_out  = $(addsuffix .out,  $(rv64si_pt_vec_tests_bin))
+
+$(rv64si_pt_vec_tests_bin): rv64si-pt-vec-%: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) -I../../env/pt -I../macros/vector -T../../env/pt/link.ld $< -o $@
+
+riscv-: \
+	$(rv64si_p_tests_dump) $(rv64si_p_tests_hex) \
+	$(rv64si_pm_tests_dump) $(rv64si_pm_tests_hex) \
+	$(rv64si_p_vec_tests_dump) $(rv64si_p_vec_tests_hex) \
+	$(rv64si_pt_vec_tests_dump) $(rv64si_pt_vec_tests_hex) \
+
+out = $(rv64si_p_tests_out) $(rv64si_pm_tests_out) $(rv64si_p_vec_tests_out)
+
+run: $(out)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	       $(out); echo;
+
+junk += \
+  $(rv64si_p_tests_bin) $(rv64si_p_tests_dump) $(rv64si_p_tests_hex) $(rv64si_p_tests_out) \
+  $(rv64si_pm_tests_bin) $(rv64si_pm_tests_dump) $(rv64si_pm_tests_hex) $(rv64si_pm_tests_out) \
+  $(rv64si_p_vec_tests_bin) $(rv64si_p_vec_tests_dump) $(rv64si_p_vec_tests_hex) $(rv64si_p_vec_tests_out) \
+  $(rv64si_pt_vec_tests_bin) $(rv64si_pt_vec_tests_dump) $(rv64si_pt_vec_tests_hex) $(rv64si_pt_vec_tests_out) \
+
+#------------------------------------------------------------
+# Default
+
+all: riscv-
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
diff --git a/isa/rv64si/coreid.S b/isa/rv64si/coreid.S
new file mode 100644
index 0000000..2b7ffc3
--- /dev/null
+++ b/isa/rv64si/coreid.S
@@ -0,0 +1,29 @@
+#*****************************************************************************
+# coreid.S
+#-----------------------------------------------------------------------------
+#
+# Test coreid.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_CASE( 2, x1, 0x0, mfpcr x1, cr12 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S
new file mode 100644
index 0000000..92ae149
--- /dev/null
+++ b/isa/rv64si/ipi.S
@@ -0,0 +1,61 @@
+#*****************************************************************************
+# ipi.S
+#-----------------------------------------------------------------------------
+#
+# Test interprocessor interrupts.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  # clear pending IPIs then enable interrupts
+  la a0, handler
+  mtpcr a0, cr3
+  mtpcr x0, cr9
+  mfpcr a0, cr0
+  li a1, 0x00ff0001
+  or a0, a0, a1
+  mtpcr a0, cr0
+
+  # wait for all cores to boot
+  la a0, coreid
+  li a1, 1
+  amoadd.w x0, a1, 0(a0)
+  lw a3, 4(x0)
+  1: lw a1, 0(a0)
+  blt a1, a3, 1b
+
+  # IPI dominoes
+  mfpcr a0, cr10
+  1: bnez a0, 1b
+  add a0, a0, 1
+  rem a0, a0, a3
+  mtpcr a0, cr8
+  1: b 1b
+
+  handler:
+  mfpcr a0, cr10
+  bnez a0, 2f
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  2: add a0, a0, 1
+  rem a0, a0, a3
+  mtpcr a0, cr8
+  1: b 1b
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+coreid: .word 0
+foo: .word 0
+
+RVTEST_DATA_END