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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-05-07 18:03:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-05-07 18:03:37 -0700 |
| commit | 675a808aab7fcaafb44290a7705f5e3006814d65 (patch) | |
| tree | 2e10bf1cc22cf44155025ad13255ac2d7ef69c14 /isa/rv64si | |
| parent | bc3505ed0b7ae151ac47f4073137b59d5fe0b5e6 (diff) | |
| download | riscv-tests-675a808aab7fcaafb44290a7705f5e3006814d65.zip riscv-tests-675a808aab7fcaafb44290a7705f5e3006814d65.tar.gz riscv-tests-675a808aab7fcaafb44290a7705f5e3006814d65.tar.bz2 | |
Add timer interrupt test
Diffstat (limited to 'isa/rv64si')
| -rw-r--r-- | isa/rv64si/Makefrag | 1 | ||||
| -rw-r--r-- | isa/rv64si/ipi.S | 6 | ||||
| -rw-r--r-- | isa/rv64si/timer.S | 63 |
3 files changed, 66 insertions, 4 deletions
diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag index 83bf22d..f40a56f 100644 --- a/isa/rv64si/Makefrag +++ b/isa/rv64si/Makefrag @@ -5,6 +5,7 @@ rv64si_sc_tests = \ coreid \ csr \ + timer \ rv64si_mc_tests = \ ipi \ diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S index 95a108a..3b03348 100644 --- a/isa/rv64si/ipi.S +++ b/isa/rv64si/ipi.S @@ -15,10 +15,8 @@ RVTEST_CODE_BEGIN la a0, handler csrw evec, a0 csrw clear_ipi, x0 - csrr a0, status - li a1, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT)) - or a0, a0, a1 - csrw status, a0 + li a0, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT)) + csrs status, a0 # wait for all cores to boot la a0, coreid diff --git a/isa/rv64si/timer.S b/isa/rv64si/timer.S new file mode 100644 index 0000000..5f755e4 --- /dev/null +++ b/isa/rv64si/timer.S @@ -0,0 +1,63 @@ +#***************************************************************************** +# ipi.S +#----------------------------------------------------------------------------- +# +# Test interprocessor interrupts. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RVTEST_CODE_BEGIN + + # clear pending IPIs then enable interrupts + li s9, 0 + la a0, handler + csrw evec, a0 + csrw count, x0 + li a1, 5000 + csrw compare, a1 + li a0, SR_EI | (1 << (IRQ_TIMER + SR_IM_SHIFT)) + csrs status, a0 + + # advance an LFSR 1000 times + li s0, 1023 + li s1, 1023 + li s4, 0 +1:srl s2,s0,3 + xor s2,s2,s0 + and s2,s2,1 + srl s0,s0,1 + sll s2,s2,9 + or s0,s2,s0 + sll s0,s0,54 + srl s0,s0,54 + add s4, s4, 1 + bne s0,s1,1b + + csrc status, SR_EI + + li TESTNUM, 2 + beqz s9, fail # make sure we took at least one interrupt + li TESTNUM, 3 + bne s4, s1, fail # make sure the LFSR period was correct + + RVTEST_PASS + + TEST_PASSFAIL + +handler: + csrr t0, cause + li t1, 0x8000000000000007 + bne t0, t1, fail + + csrr t0, compare + addi t0, t0, 99 + csrw compare, t0 + + add s9, s9, 1 + + sret + +RVTEST_CODE_END |