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authorAndrew Waterman <waterman@cs.berkeley.edu>2013-08-23 20:02:02 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2013-08-23 20:04:30 -0700
commit5fe2ce69dcd1d0ddb42c4edffac7ab11d939ca45 (patch)
tree1c76b45e4b7cf966f5d0d3b943d66b04c4f95c21 /isa/rv64si
parent5b13eb6cd5aa3e73fb477414f1866e7b9cbeaf3f (diff)
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Reflect changes to ISA
Conflicts: isa/Makefile
Diffstat (limited to 'isa/rv64si')
-rw-r--r--isa/rv64si/coreid.S2
-rw-r--r--isa/rv64si/ipi.S18
2 files changed, 10 insertions, 10 deletions
diff --git a/isa/rv64si/coreid.S b/isa/rv64si/coreid.S
index 2b7ffc3..47336db 100644
--- a/isa/rv64si/coreid.S
+++ b/isa/rv64si/coreid.S
@@ -15,7 +15,7 @@ RVTEST_CODE_BEGIN
# Basic tests
#-------------------------------------------------------------
- TEST_CASE( 2, x1, 0x0, mfpcr x1, cr12 );
+ TEST_CASE( 2, x1, 0x0, mfpcr x1, hartid );
TEST_PASSFAIL
diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S
index 92ae149..8db0163 100644
--- a/isa/rv64si/ipi.S
+++ b/isa/rv64si/ipi.S
@@ -13,12 +13,12 @@ RVTEST_CODE_BEGIN
# clear pending IPIs then enable interrupts
la a0, handler
- mtpcr a0, cr3
- mtpcr x0, cr9
- mfpcr a0, cr0
- li a1, 0x00ff0001
+ mtpcr a0, evec
+ mtpcr x0, clear_ipi
+ mfpcr a0, status
+ li a1, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
or a0, a0, a1
- mtpcr a0, cr0
+ mtpcr a0, status
# wait for all cores to boot
la a0, coreid
@@ -29,15 +29,15 @@ RVTEST_CODE_BEGIN
blt a1, a3, 1b
# IPI dominoes
- mfpcr a0, cr10
+ mfpcr a0, hartid
1: bnez a0, 1b
add a0, a0, 1
rem a0, a0, a3
- mtpcr a0, cr8
+ mtpcr a0, send_ipi
1: b 1b
handler:
- mfpcr a0, cr10
+ mfpcr a0, hartid
bnez a0, 2f
RVTEST_PASS
@@ -45,7 +45,7 @@ RVTEST_CODE_BEGIN
2: add a0, a0, 1
rem a0, a0, a3
- mtpcr a0, cr8
+ mtpcr a0, send_ipi
1: b 1b
RVTEST_CODE_END