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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-02 22:33:37 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-03 11:03:59 -0800 |
| commit | 4d1491df727e9aeb5fdfeac25c22eaf24cafb908 (patch) | |
| tree | 3b3639675a9eb006a0eb7cb35d89a6ba34006cea /isa/rv64si/csr.S | |
| parent | a0a3ae4841308010c6437e0f47467af97a140cda (diff) | |
| download | riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.zip riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.tar.gz riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.tar.bz2 | |
Some S-mode tests really only belong in M-mode
Diffstat (limited to 'isa/rv64si/csr.S')
| -rw-r--r-- | isa/rv64si/csr.S | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index af0b756..d0c6724 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -34,7 +34,10 @@ RVTEST_CODE_BEGIN TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch); # Make sure writing the cycle counter causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0); +#endif # jump to user land li t0, SSTATUS_SPP @@ -45,7 +48,12 @@ RVTEST_CODE_BEGIN 1: # Make sure reading status in user mode causes an exception. - TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus); + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus) +#else + TEST_CASE(11, x0, 0, nop) +#endif # Exit by doing a syscall. TEST_CASE(12, x0, 1, scall) |