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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-26 19:53:25 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-08-26 20:26:52 -0700 |
| commit | 05f70dc4925262713355bba0cedfd3f5c0d485e5 (patch) | |
| tree | ad107b51d56bc9aa18cb810cd71d51dddfb5b5a7 /isa/rv64si/csr.S | |
| parent | 5ad886f909376920d345c7cf1f7b70c7ef37392f (diff) | |
| download | riscv-tests-05f70dc4925262713355bba0cedfd3f5c0d485e5.zip riscv-tests-05f70dc4925262713355bba0cedfd3f5c0d485e5.tar.gz riscv-tests-05f70dc4925262713355bba0cedfd3f5c0d485e5.tar.bz2 | |
Update to new breakpoint & counter spec
Diffstat (limited to 'isa/rv64si/csr.S')
| -rw-r--r-- | isa/rv64si/csr.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S index 68f6fb1..1f7bb77 100644 --- a/isa/rv64si/csr.S +++ b/isa/rv64si/csr.S @@ -42,12 +42,6 @@ RVTEST_CODE_BEGIN beqz a0, finish # if no user mode, skip the rest of these checks #endif - # Make sure writing the cycle counter causes an exception. - # Don't run in supervisor, as we don't delegate illegal instruction traps. -#ifdef __MACHINE_MODE - TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0); -#endif - # jump to user land li t0, SSTATUS_SPP csrc sstatus, t0 @@ -56,6 +50,12 @@ RVTEST_CODE_BEGIN sret 1: + # Make sure writing the cycle counter causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0); +#endif + # Make sure reading status in user mode causes an exception. # Don't run in supervisor, as we don't delegate illegal instruction traps. #ifdef __MACHINE_MODE |