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authorAndrew Waterman <waterman@cs.berkeley.edu>2015-05-09 16:39:39 -0700
committerAndrew Waterman <waterman@cs.berkeley.edu>2015-05-09 16:39:39 -0700
commita60626553be99d69f879464dbeb71ffe1ff80c75 (patch)
tree9addb6b177536179dc4d9b72b510cbe7f0f70a78 /isa/rv64mi
parent5ce97df1c97b4ef39b94041350b910d12f782328 (diff)
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Update to privileged architecture version 1.7
Diffstat (limited to 'isa/rv64mi')
-rw-r--r--isa/rv64mi/Makefrag1
-rw-r--r--isa/rv64mi/dirty.S4
-rw-r--r--isa/rv64mi/ipi.S5
-rw-r--r--isa/rv64mi/mcsr.S30
4 files changed, 36 insertions, 4 deletions
diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag
index db40dc1..52f6462 100644
--- a/isa/rv64mi/Makefrag
+++ b/isa/rv64mi/Makefrag
@@ -5,6 +5,7 @@
rv64mi_sc_tests = \
dirty \
csr \
+ mcsr \
illegal \
ma_fetch \
ma_addr \
diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 1cf429a..2be4921 100644
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -74,9 +74,9 @@ die:
.data
.align 12
-page_table_1: .dword PTE_TYPE_US_SRX
+page_table_1: .dword PTE_V | PTE_TYPE_URX_SRX
dummy: .dword 0
.align 12
-page_table_2: .dword PTE_TYPE_US_SRWX
+page_table_2: .dword PTE_V | PTE_TYPE_URWX_SRWX
RVTEST_CODE_END
diff --git a/isa/rv64mi/ipi.S b/isa/rv64mi/ipi.S
index 326476d..457a9cd 100644
--- a/isa/rv64mi/ipi.S
+++ b/isa/rv64mi/ipi.S
@@ -15,6 +15,7 @@ RVTEST_CODE_BEGIN
# enable interrupts
csrs mstatus, MSTATUS_IE
+ csrs mie, MIP_MSIP
# get a unique core id
la a0, coreid
@@ -30,7 +31,7 @@ RVTEST_CODE_BEGIN
bltu a1, a3, 1b
# IPI dominoes
- csrr a0, hartid
+ csrr a0, mhartid
1: bnez a0, 1b
add a0, a0, 1
rem a0, a0, a3
@@ -38,7 +39,7 @@ RVTEST_CODE_BEGIN
1: j 1b
mtvec_handler:
- csrr a0, hartid
+ csrr a0, mhartid
bnez a0, 2f
RVTEST_PASS
diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
new file mode 100644
index 0000000..c1e2cd3
--- /dev/null
+++ b/isa/rv64mi/mcsr.S
@@ -0,0 +1,30 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mcsr.S
+#-----------------------------------------------------------------------------
+#
+# Test various M-mode CSRs.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+ # Check that mcpuid reports RV64
+ TEST_CASE(2, a0, 0x2, csrr a0, mcpuid; srl a0, a0, 62)
+
+ # Check that mhartid reports 0
+ TEST_CASE(3, a0, 0x0, csrr a0, mhartid)
+
+ # Check that mimpid reports UC Berkeley
+ TEST_CASE(4, a0, 0x1, csrr a0, mimpid; sll a0, a0, 48; srl a0, a0, 48)
+
+ # Check that mtvec reports DEFAULT_MTVEC
+ TEST_CASE(5, a0, DEFAULT_MTVEC, csrr a0, mtvec)
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END