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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-02 22:33:37 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-03 11:03:59 -0800 |
| commit | 4d1491df727e9aeb5fdfeac25c22eaf24cafb908 (patch) | |
| tree | 3b3639675a9eb006a0eb7cb35d89a6ba34006cea /isa/rv64mi/illegal.S | |
| parent | a0a3ae4841308010c6437e0f47467af97a140cda (diff) | |
| download | riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.zip riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.tar.gz riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.tar.bz2 | |
Some S-mode tests really only belong in M-mode
Diffstat (limited to 'isa/rv64mi/illegal.S')
| -rw-r--r-- | isa/rv64mi/illegal.S | 40 |
1 files changed, 36 insertions, 4 deletions
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S index c5ccffd..ecb3088 100644 --- a/isa/rv64mi/illegal.S +++ b/isa/rv64mi/illegal.S @@ -1,8 +1,40 @@ # See LICENSE for license details. +#***************************************************************************** +# illegal.S +#----------------------------------------------------------------------------- +# +# Test illegal instruction trap. +# + #include "riscv_test.h" -#undef RVTEST_RV64S -#define RVTEST_RV64S RVTEST_RV64M -#define __MACHINE_MODE +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + li TESTNUM, 2 + .word 0 + j fail + + j pass + + TEST_PASSFAIL + +mtvec_handler: + li t1, CAUSE_ILLEGAL_INSTRUCTION + csrr t0, mcause + bne t0, t1, fail + csrr t0, mepc + addi t0, t0, 8 + csrw mepc, t0 + sret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA -#include "../rv64si/illegal.S" +RVTEST_DATA_END |