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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-01 23:17:17 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-01 23:17:17 -0800 |
| commit | 367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c (patch) | |
| tree | 08f0c0c16a63ebe581681ca5abe9ea93d8a88915 /isa/rv32um/mul.S | |
| parent | b4e820b5a0007d5ca8ab1a5de2327d247a81a9aa (diff) | |
| download | riscv-tests-367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c.zip riscv-tests-367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c.tar.gz riscv-tests-367a13f0c2bd8d6e5a5ed71dbd3c9d46c6e21c3c.tar.bz2 | |
Test FMIN/FMAX NaN behavior
See https://github.com/riscv/riscv-isa-sim/issues/76
Diffstat (limited to 'isa/rv32um/mul.S')
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