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| author | Andrew Waterman <andrew@sifive.com> | 2021-06-01 23:52:43 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-06-01 23:52:43 -0700 |
| commit | 1b2c3ea84a7f8d8a833fca4d2b9aebb7d1ba4269 (patch) | |
| tree | e020f723e7ecfb53424bc5f940dc9d97253d5acf /isa/rv32uf/fclass.S | |
| parent | 3e175a094ff15ea28ae173af8f00a36c5ed9d296 (diff) | |
| download | riscv-tests-1b2c3ea84a7f8d8a833fca4d2b9aebb7d1ba4269.zip riscv-tests-1b2c3ea84a7f8d8a833fca4d2b9aebb7d1ba4269.tar.gz riscv-tests-1b2c3ea84a7f8d8a833fca4d2b9aebb7d1ba4269.tar.bz2 | |
Enable access to cycle counter before trying to write it
There are two reasons that writing the cycle counter might trap:
- Because it's a read-only CSR
- Because mcounteren.CY=0 or scounteren.CY=0
We want to make sure we're testing the first property, so set up
the other bits accordingly.
Diffstat (limited to 'isa/rv32uf/fclass.S')
0 files changed, 0 insertions, 0 deletions