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| author | Torbjørn <tovine@users.noreply.github.com> | 2017-11-27 06:56:53 +0100 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2017-11-26 21:56:53 -0800 |
| commit | 49f478416cec9f73801fdc5dedf9955494be8c66 (patch) | |
| tree | ee07276de133354d01ba5efbf02514e2e841b25f /isa/rv32ud/ldst.S | |
| parent | 018aea17aca9abb6221e1a59d943ecdd386cc8ec (diff) | |
| download | riscv-tests-49f478416cec9f73801fdc5dedf9955494be8c66.zip riscv-tests-49f478416cec9f73801fdc5dedf9955494be8c66.tar.gz riscv-tests-49f478416cec9f73801fdc5dedf9955494be8c66.tar.bz2 | |
Rv32ud tests (#108)
* Probably implemented the changes required to support fadd test for rv32ud
* Created test files in rv32ud, implemented working(?) test for ldst
* fclass, fcvt_w, fmin and recoding seem to be working now
* Got fdiv (and sqrt) tests working
* fmadd tests seem to work
* fcmp works
* [WIP] fcvt working, but lacks a 32-bit implementation of the final test
* Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST
* Added Makefrag for rv32ud tests and included in main isa Makefile
* Don't run 64-bit tests if the defined XLEN is 32
Diffstat (limited to 'isa/rv32ud/ldst.S')
| -rw-r--r-- | isa/rv32ud/ldst.S | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/isa/rv32ud/ldst.S b/isa/rv32ud/ldst.S new file mode 100644 index 0000000..e39fe30 --- /dev/null +++ b/isa/rv32ud/ldst.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32UF +RVTEST_CODE_BEGIN + + la s0, tdat + TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END |