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| author | Chih-Min Chao <48193236+chihminchao@users.noreply.github.com> | 2022-12-08 14:27:21 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-07 22:27:21 -0800 |
| commit | 5cbc01f45d9876ec84e8229d4c3898c96597e431 (patch) | |
| tree | 78ccb09b42cc6c2ef9f58c756450ba06ca8b8c16 /isa/rv32uc | |
| parent | 907f1e5b67daedef0acbefb2102b82a23f9abfad (diff) | |
| download | riscv-tests-5cbc01f45d9876ec84e8229d4c3898c96597e431.zip riscv-tests-5cbc01f45d9876ec84e8229d4c3898c96597e431.tar.gz riscv-tests-5cbc01f45d9876ec84e8229d4c3898c96597e431.tar.bz2 | |
zicntr: separate cycle/instret accessibility test (#439)
It is allowed that M-mode only implementation could skip cycle/instret
if the Zicntr is not included.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'isa/rv32uc')
0 files changed, 0 insertions, 0 deletions