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| author | Colin Schmidt <colins@eecs.berkeley.edu> | 2016-02-29 10:00:15 -0800 |
|---|---|---|
| committer | Colin Schmidt <colins@eecs.berkeley.edu> | 2016-02-29 10:54:27 -0800 |
| commit | af7bcec998b72b2b91180c83b45151201fa1c150 (patch) | |
| tree | e632d433c598b38499df4e299b893800ad00e428 /isa/rv32ua/amominu_w.S | |
| parent | 9e63c8544ea2e0aea6778defb7b535dbb87b7205 (diff) | |
| download | riscv-tests-af7bcec998b72b2b91180c83b45151201fa1c150.zip riscv-tests-af7bcec998b72b2b91180c83b45151201fa1c150.tar.gz riscv-tests-af7bcec998b72b2b91180c83b45151201fa1c150.tar.bz2 | |
Separate M, and A from I. Allow disabling of M,A,Ftravis-dev
This allows riscv-tests to be built with a compiler
that supports not just RVG.
Diffstat (limited to 'isa/rv32ua/amominu_w.S')
| -rw-r--r-- | isa/rv32ua/amominu_w.S | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/isa/rv32ua/amominu_w.S b/isa/rv32ua/amominu_w.S new file mode 100644 index 0000000..ce06e1c --- /dev/null +++ b/isa/rv32ua/amominu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 |