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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-02 22:33:37 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-03-03 11:03:59 -0800 |
| commit | 4d1491df727e9aeb5fdfeac25c22eaf24cafb908 (patch) | |
| tree | 3b3639675a9eb006a0eb7cb35d89a6ba34006cea /isa/rv32mi/shamt.S | |
| parent | a0a3ae4841308010c6437e0f47467af97a140cda (diff) | |
| download | riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.zip riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.tar.gz riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.tar.bz2 | |
Some S-mode tests really only belong in M-mode
Diffstat (limited to 'isa/rv32mi/shamt.S')
| -rw-r--r-- | isa/rv32mi/shamt.S | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/isa/rv32mi/shamt.S b/isa/rv32mi/shamt.S new file mode 100644 index 0000000..2c92412 --- /dev/null +++ b/isa/rv32mi/shamt.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# csr.S +#----------------------------------------------------------------------------- +# +# Test CSRRx and CSRRxI instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32M +RVTEST_CODE_BEGIN + + # Make sure slli with shamt[4] set is legal. + TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); + + # Make sure slli with shamt[5] set is not legal. + TEST_CASE( 3, x0, 1, slli a0, a0, 32); + + TEST_PASSFAIL + +mtvec_handler: + # Trapping on test 3 is good. + # Note that since the test didn't complete, TESTNUM is smaller by 1. + li t0, 2 + bne TESTNUM, t0, fail + + # Make sure CAUSE indicates an illegal instructino. + csrr t0, mcause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, fail + j pass + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |