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| author | Nadime Barhoumi <nadime@riscv.org> | 2026-04-24 16:46:28 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2026-04-24 13:46:28 -0700 |
| commit | 0bbecd1a01c61a16ad45fdfd89f29ebfdb493d1d (patch) | |
| tree | 44c99b561b63858df13f11463a140352d22d695a /isa/hypervisor/Makefrag | |
| parent | 933a897d8631773f385d45938facc466dddc7514 (diff) | |
| download | riscv-tests-master.tar.gz riscv-tests-master.tar.bz2 riscv-tests-master.zip | |
Adds four RV64 hypervisor tests exercising implicit G-stage faults raised
during VS-stage page table walks:
- 2-stage_translation_implicit_load_error
- 2-stage_translation_implicit_load_error_hs
- 2-stage_translation_implicit_store_error
- 2-stage_translation_implicit_store_error_hs
The load variants trigger the fault by leaving the G-stage PTE invalid
(no PTE_V), causing the implicit PTE read during the VS-stage walk to
fault. The store variants omit PTE_W on the G-stage PTE, so G-stage
grants read but denies write, causing the implicit PTE store for the
A/D writeback to fail. These require hardware A/D updates, which occur
when Svadu is enabled via ADUE.
Each test checks mcause/scause, mtval/stval, and mtval2/htval and
verifies that mtinst/htinst contains the expected pseudoinstruction:
- 0x3000 — 64-bit implicit VS-stage PTE load
- 0x3020 — 64-bit implicit VS-stage PTE store
Diffstat (limited to 'isa/hypervisor/Makefrag')
| -rw-r--r-- | isa/hypervisor/Makefrag | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/isa/hypervisor/Makefrag b/isa/hypervisor/Makefrag index 08f711a..2a48722 100644 --- a/isa/hypervisor/Makefrag +++ b/isa/hypervisor/Makefrag @@ -4,5 +4,7 @@ hypervisor_sc_tests = \ 2-stage_translation \ + 2-stage_translation_implicit_load_error \ + 2-stage_translation_implicit_load_error_hs \ hypervisor_p_tests = $(addprefix hypervisor-p-, $(hypervisor_sc_tests)) |